static mali_bool init_mali_clock(void) { mali_bool ret = MALI_TRUE; if (mali_clock != 0) return ret; // already initialized mali_dvfs_lock = _mali_osk_lock_init(_MALI_OSK_LOCKFLAG_NONINTERRUPTABLE | _MALI_OSK_LOCKFLAG_ONELOCK, 0, 0); if (mali_dvfs_lock == NULL) return _MALI_OSK_ERR_FAULT; if (mali_clk_set_rate(mali_gpu_clk, GPU_MHZ) == MALI_FALSE) { ret = MALI_FALSE; goto err_clock_get; } MALI_PRINT(("init_mali_clock mali_clock %p \n", mali_clock)); #ifdef CONFIG_REGULATOR #if USING_MALI_PMM g3d_regulator = regulator_get(&mali_gpu_device.dev, "vdd_g3d"); #else g3d_regulator = regulator_get(NULL, "vdd_g3d"); #endif if (IS_ERR(g3d_regulator)) { MALI_PRINT( ("MALI Error : failed to get vdd_g3d\n")); ret = MALI_FALSE; goto err_regulator; } regulator_enable(g3d_regulator); MALI_DEBUG_PRINT(1, ("= regulator_enable -> use cnt: %d \n",mali_regulator_get_usecount())); mali_regulator_set_voltage(mali_gpu_vol, mali_gpu_vol); #endif MALI_DEBUG_PRINT(2, ("MALI Clock is set at mali driver\n")); MALI_DEBUG_PRINT(3,("::clk_put:: %s mali_parent_clock - normal\n", __FUNCTION__)); MALI_DEBUG_PRINT(3,("::clk_put:: %s mpll_clock - normal\n", __FUNCTION__)); mali_clk_put(MALI_FALSE); gpu_power_state = 0; bPoweroff = 1; return MALI_TRUE; #ifdef CONFIG_REGULATOR err_regulator: regulator_put(g3d_regulator); #endif err_clock_get: mali_clk_put(MALI_TRUE); return ret; }
void mali_clk_set_rate(unsigned int clk, unsigned int mhz) { int err; unsigned long rate = (unsigned long)clk * (unsigned long)mhz; _mali_osk_lock_wait(mali_freq_lock, _MALI_OSK_LOCKMODE_RW); MALI_DEBUG_PRINT(3, ("Mali platform: Setting frequency to %d mhz\n", clk)); if (mali_clk_get() == MALI_FALSE) { _mali_osk_lock_signal(mali_freq_lock, _MALI_OSK_LOCKMODE_RW); return; } err = clk_set_rate(mali_clock, rate); if (err) MALI_PRINT_ERROR(("Failed to set Mali clock: %d\n", err)); rate = clk_get_rate(mali_clock); GPU_MHZ = mhz; mali_gpu_clk = rate / mhz; MALI_PRINT(("Mali freq %dMhz\n", rate / mhz)); mali_clk_put(MALI_FALSE); _mali_osk_lock_signal(mali_freq_lock, _MALI_OSK_LOCKMODE_RW); }
static mali_bool deinit_mali_clock(void) { if (mali_clock == 0) return MALI_TRUE; mali_clk_put(MALI_TRUE); return MALI_TRUE; }
mali_bool mali_clk_set_rate(unsigned int clk, unsigned int mhz) { unsigned long rate = 0; mali_bool bis_vpll = MALI_FALSE; #ifdef CONFIG_VPLL_USE_FOR_TVENC bis_vpll = MALI_TRUE; #endif _mali_osk_lock_wait(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW); if (mali_clk_get(bis_vpll) == MALI_FALSE) return MALI_FALSE; rate = (unsigned long)clk * (unsigned long)mhz; MALI_DEBUG_PRINT(3,("= clk_set_rate : %d , %d \n",clk, mhz )); if (bis_vpll) { clk_set_rate(fout_vpll_clock, (unsigned int)clk * GPU_MHZ); clk_set_parent(vpll_src_clock, ext_xtal_clock); clk_set_parent(sclk_vpll_clock, fout_vpll_clock); clk_set_parent(mali_parent_clock, sclk_vpll_clock); clk_set_parent(mali_clock, mali_parent_clock); } else { clk_set_parent(mali_parent_clock, mpll_clock); clk_set_parent(mali_clock, mali_parent_clock); } if (clk_enable(mali_clock) < 0) return MALI_FALSE; clk_set_rate(mali_clock, rate); rate = clk_get_rate(mali_clock); if (bis_vpll) mali_gpu_clk = (int)(rate / mhz); else mali_gpu_clk = (int)((rate + 500000) / mhz); GPU_MHZ = mhz; MALI_DEBUG_PRINT(3,("= clk_get_rate: %d \n",mali_gpu_clk)); mali_clk_put(MALI_FALSE); _mali_osk_lock_signal(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW); return MALI_TRUE; }
static mali_bool deinit_mali_clock(void) { if (mali_clock == 0) return MALI_TRUE; #ifdef CONFIG_REGULATOR if (g3d_regulator) { regulator_put(g3d_regulator); g3d_regulator = NULL; } #endif mali_clk_put(MALI_TRUE); return MALI_TRUE; }
/***************************************************************************** function name : deinit_mali_clock_regulator description : mali clk and regulator deinit input vars : void output vars : NA return value : mali_bool calls : mali_clk_put,mali_regulator_disable called : mali_platform_deinit history : 1.data : 04/03/2014 author : s00250033 modify : new *****************************************************************************/ static mali_bool deinit_mali_clock_regulator(void) { if ( (NULL == mali_clock) || (NULL == mali_regulator)) { return MALI_TRUE; } /* powerdown */ mali_platform_powerdown(); /* CLK */ mali_clk_put(); /* REGULATOR */ regulator_put(mali_regulator); return MALI_TRUE; }
mali_bool mali_clk_set_rate(unsigned int clk, unsigned int mhz) { unsigned long rate = 0; mali_bool bis_vpll = MALI_TRUE; #ifndef CONFIG_VPLL_USE_FOR_TVENC bis_vpll = MALI_TRUE; #endif #if !MALI_DVFS_ENABLED clk = mali_gpu_clk; #endif trace_printk("SPI_GPUFREQ_%uMHz\n", mali_gpu_clk); _mali_osk_lock_wait(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW); if (mali_clk_get(bis_vpll) == MALI_FALSE) return MALI_FALSE; rate = (unsigned long)clk * (unsigned long)mhz; MALI_DEBUG_PRINT(3,("= clk_set_rate : %d , %d \n",clk, mhz )); if (bis_vpll) { clk_set_rate(fout_vpll_clock, (unsigned int)clk * GPU_MHZ); clk_set_parent(vpll_src_clock, ext_xtal_clock); clk_set_parent(sclk_vpll_clock, fout_vpll_clock); clk_set_parent(mali_parent_clock, sclk_vpll_clock); clk_set_parent(mali_clock, mali_parent_clock); } else { clk_set_parent(mali_parent_clock, mpll_clock); clk_set_parent(mali_clock, mali_parent_clock); } if (clk_enable(mali_clock) < 0) return MALI_FALSE; #if MALI_TIMELINE_PROFILING_ENABLED _mali_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE | MALI_PROFILING_EVENT_CHANNEL_SOFTWARE | MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_FREQ, rate, 0, 0, 0, 0); #endif clk_set_rate(mali_clock, rate); rate = clk_get_rate(mali_clock); #if MALI_TIMELINE_PROFILING_ENABLED _mali_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE | MALI_PROFILING_EVENT_CHANNEL_SOFTWARE | MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_FREQ, rate, 1, 0, 0, 0); #endif if (bis_vpll) mali_gpu_clk = (int)(rate / mhz); else mali_gpu_clk = (int)((rate + 500000) / mhz); GPU_MHZ = mhz; MALI_DEBUG_PRINT(3,("= clk_get_rate: %d \n",mali_gpu_clk)); mali_clk_put(MALI_FALSE); _mali_osk_lock_signal(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW); return MALI_TRUE; }
static mali_bool init_mali_clock(void) { mali_bool ret = MALI_TRUE; nPowermode = MALI_POWER_MODE_DEEP_SLEEP; if (mali_clock != 0) return ret; /* already initialized */ mali_dvfs_lock = _mali_osk_lock_init(_MALI_OSK_LOCKFLAG_NONINTERRUPTABLE | _MALI_OSK_LOCKFLAG_ONELOCK, 0, 0); if (mali_dvfs_lock == NULL) return _MALI_OSK_ERR_FAULT; if (!mali_clk_get()) { MALI_PRINT(("Error: Failed to get Mali clock\n")); goto err_clk; } clk_set_parent(vpll_src_clock, ext_xtal_clock); clk_set_parent(sclk_vpll_clock, fout_vpll_clock); clk_set_parent(mali_parent_clock, sclk_vpll_clock); clk_set_parent(mali_clock, mali_parent_clock); if (!atomic_read(&clk_active)) { if (clk_enable(mali_clock) < 0) { MALI_PRINT(("Error: Failed to enable clock\n")); goto err_clk; } atomic_set(&clk_active, 1); } mali_clk_set_rate((unsigned int)mali_gpu_clk, GPU_MHZ); MALI_PRINT(("init_mali_clock mali_clock %x\n", mali_clock)); #ifdef CONFIG_REGULATOR g3d_regulator = regulator_get(NULL, "vdd_g3d"); if (IS_ERR(g3d_regulator)) { MALI_PRINT( ("MALI Error : failed to get vdd_g3d\n")); ret = MALI_FALSE; goto err_regulator; } mali_gpu_vol = get_match_volt(ID_G3D, mali_gpu_clk * GPU_ASV_VOLT); mali_runtime_resume.vol = get_match_volt(ID_G3D, mali_runtime_resume.clk * GPU_ASV_VOLT); regulator_enable(g3d_regulator); mali_regulator_set_voltage(mali_gpu_vol, mali_gpu_vol); exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_runtime_resume.clk * GPU_ASV_VOLT)); #endif #if defined(CONFIG_MALI400_PROFILING) _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE| MALI_PROFILING_EVENT_CHANNEL_GPU| MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, mali_gpu_clk, mali_gpu_vol/1000, 0, 0, 0); #endif mali_clk_put(MALI_FALSE); return MALI_TRUE; #ifdef CONFIG_REGULATOR err_regulator: regulator_put(g3d_regulator); #endif err_clk: mali_clk_put(MALI_TRUE); return ret; }
static int mali_devfreq_target(struct device *dev, unsigned long *freq, u32 flags) { unsigned int nextStatus = (unsigned int)*freq; unsigned int curStatus = 0; curStatus = maliDvfsStatus.currentStep; MALI_DEBUG_PRINT(4, ("= curStatus %d, nextStatus %d, maliDvfsStatus.currentStep %d\n", curStatus, nextStatus, maliDvfsStatus.currentStep)); /*if next status is same with current status, don't change anything*/ if (curStatus != nextStatus) { #if MALI_DVFS_CLK_DEBUG unsigned int *pRegMaliClkDiv; unsigned int *pRegMaliMpll; #endif if (nextStatus > curStatus) { #ifdef CONFIG_MALI_DVFS update_time_in_state(curStatus); #endif #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT), get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT)); exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT)); #endif /*change the clock*/ mali_clk_set_rate(mali_dvfs[nextStatus].clock, mali_dvfs[nextStatus].freq); } else if (nextStatus < curStatus) { #ifdef CONFIG_MALI_DVFS update_time_in_state(curStatus); #endif /*change the clock*/ mali_clk_set_rate(mali_dvfs[nextStatus].clock, mali_dvfs[nextStatus].freq); #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT), get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT)); exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT)); #endif } else return 0; #if defined(CONFIG_MALI400_PROFILING) _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE| MALI_PROFILING_EVENT_CHANNEL_GPU| MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, mali_gpu_clk, mali_gpu_vol/1000, 0, 0, 0); #endif mali_clk_put(MALI_FALSE); #if MALI_DVFS_CLK_DEBUG pRegMaliClkDiv = ioremap(0x1003c52c, 32); pRegMaliMpll = ioremap(0x1003c22c, 32); MALI_PRINT(("Mali MPLL reg:%d, CLK DIV: %d \n", *pRegMaliMpll, *pRegMaliClkDiv)); #endif set_mali_dvfs_current_step(nextStatus); /*for future use*/ maliDvfsStatus.pCurrentDvfs = &mali_dvfs[nextStatus]; #if CPUFREQ_LOCK_DURING_440 /* lock/unlock CPU freq by Mali */ if (mali_dvfs[nextStatus].clock >= 440) cpufreq_lock_by_mali(400); else cpufreq_unlock_by_mali(); #endif /*wait until clock and voltage is stablized*/ mali_platform_wating(MALI_DVFS_WATING); /*msec*/ } return 0; }
void mali_clk_set_rate(unsigned int clk, unsigned int mhz) { int err; unsigned long rate = (unsigned long)clk * (unsigned long)mhz; unsigned int read_val; _mali_osk_lock_wait(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW); MALI_DEBUG_PRINT(3, ("Mali platform: Setting frequency to %d mhz\n", clk)); if (mali_clk_get() == MALI_FALSE) { _mali_osk_lock_signal(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW); return; } clk_set_parent(mali_parent_clock, mout_epll_clock); do { cpu_relax(); read_val = __raw_readl(EXYNOS4_CLKMUX_STAT_G3D0); } while (((read_val >> 4) & 0x7) != 0x1); MALI_DEBUG_PRINT(3, ("Mali platform: set to EPLL EXYNOS4270_CLKMUX_STAT_G3D0 : 0x%08x\n", __raw_readl(EXYNOS4270_CLKMUX_STAT_G3D0))); err = clk_set_parent(sclk_vpll_clock, ext_xtal_clock); if (err) MALI_PRINT_ERROR(("sclk_vpll set parent to ext_xtal failed\n")); MALI_DEBUG_PRINT(3, ("Mali platform: set_parent_vpll : %8.x \n", (__raw_readl(EXYNOS4_CLKSRC_TOP0) >> 8) & 0x1)); clk_set_rate(fout_vpll_clock, (unsigned int)clk * GPU_MHZ); clk_set_parent(vpll_src_clock, ext_xtal_clock); err = clk_set_parent(sclk_vpll_clock, fout_vpll_clock); if (err) MALI_PRINT_ERROR(("sclk_vpll set parent to fout_vpll failed\n")); MALI_DEBUG_PRINT(3, ("Mali platform: set_parent_vpll : %8.x \n", (__raw_readl(EXYNOS4_CLKSRC_TOP0) >> 8) & 0x1)); clk_set_parent(mali_parent_clock, sclk_vpll_clock); do { cpu_relax(); read_val = __raw_readl(EXYNOS4_CLKMUX_STAT_G3D0); } while (((read_val >> 4) & 0x7) != 0x2); MALI_DEBUG_PRINT(3, ("SET to VPLL EXYNOS4270_CLKMUX_STAT_G3D0 : 0x%08x\n", __raw_readl(EXYNOS4270_CLKMUX_STAT_G3D0))); clk_set_parent(mali_clock, mali_parent_clock); if (!atomic_read(&clk_active)) { if (clk_enable(mali_clock) < 0) { _mali_osk_lock_signal(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW); return; } atomic_set(&clk_active, 1); } err = clk_set_rate(mali_clock, rate); if (err) MALI_PRINT_ERROR(("Failed to set Mali clock: %d\n", err)); rate = clk_get_rate(mali_clock); MALI_DEBUG_PRINT(1, ("Mali frequency %d\n", rate / mhz)); GPU_MHZ = mhz; mali_gpu_clk = clk; mali_clk_put(MALI_FALSE); _mali_osk_lock_signal(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW); }
static mali_bool init_mali_clock(void) { int err = 0; mali_bool ret = MALI_TRUE; nPowermode = MALI_POWER_MODE_DEEP_SLEEP; if (mali_clock != 0) return ret; /* already initialized */ mali_freq_lock = _mali_osk_lock_init(_MALI_OSK_LOCKFLAG_NONINTERRUPTABLE | _MALI_OSK_LOCKFLAG_ONELOCK, 0, 0); if (mali_freq_lock == NULL) return _MALI_OSK_ERR_FAULT; if (!mali_clk_get()) { MALI_PRINT(("Error: Failed to get Mali clock\n")); goto err_clk; } #ifndef CONFIG_EXYNOS3_VPLL err = clk_set_parent(mali_mout0_clock, sclk_mpll_pre_div_clock); if (err) MALI_PRINT_ERROR(("mali_mout0_clock set parent to sclk_mpll_pre_div_clock failed\n")); err = clk_set_parent(mali_clock, mali_mout0_clock); if (err) MALI_PRINT_ERROR(("mali_clock set parent to mali_mout0_clock failed\n")); #else err = clk_set_rate(fout_vpll_clock, (unsigned int)mali_gpu_clk * GPU_MHZ); if (err > 0) MALI_PRINT_ERROR(("Failed to set fout_vpll clock: %d\n", err)); err = clk_set_parent(vpll_src_clock, ext_xtal_clock); if (err) MALI_PRINT_ERROR(("vpll_src_clock set parent to ext_xtal_clock failed\n")); err = clk_set_parent(sclk_vpll_clock, fout_vpll_clock); if (err) MALI_PRINT_ERROR(("sclk_vpll_clock set parent to fout_vpll_clock failed\n")); err = clk_set_parent(mali_mout1_clock, sclk_vpll_clock); if (err) MALI_PRINT_ERROR(("mali_mout1_clock set parent to sclk_vpll_clock failed\n")); err = clk_set_parent(mali_clock, mali_mout1_clock); if (err) MALI_PRINT_ERROR(("mali_clock set parent to mali_mout1_clock failed\n")); #endif if (!atomic_read(&clk_active)) { if (clk_enable(mali_clock) < 0) { MALI_PRINT(("Error: Failed to enable clock\n")); goto err_clk; } atomic_set(&clk_active, 1); } mali_clk_set_rate((unsigned int)mali_gpu_clk, GPU_MHZ); mali_clk_put(MALI_FALSE); return MALI_TRUE; err_clk: mali_clk_put(MALI_TRUE); return ret; }
mali_bool mali_clk_set_rate(unsigned int clk, unsigned int mhz) { unsigned long rate = 0; mali_bool bis_vpll = MALI_TRUE; #ifndef CONFIG_VPLL_USE_FOR_TVENC bis_vpll = MALI_TRUE; #endif #ifndef CONFIG_MALI_DVFS clk = mali_gpu_clk; #endif _mali_osk_mutex_wait(mali_dvfs_lock); if (mali_clk_get(bis_vpll) == MALI_FALSE) { printk("~~~~~~~~ERROR: [%s] %d\n ",__func__,__LINE__); return MALI_FALSE; } rate = (unsigned long)clk * (unsigned long)mhz; MALI_DEBUG_PRINT(2,("= clk_set_rate : %d , %d \n",clk, mhz )); if (bis_vpll) { clk_set_rate(fout_vpll_clock, (unsigned int)clk * GPU_MHZ); //clk_set_parent(vpll_src_clock, ext_xtal_clock); clk_set_parent(sclk_vpll_clock, fout_vpll_clock); clk_set_parent(mali_parent_clock, sclk_vpll_clock); clk_set_parent(mali_clock, mali_parent_clock); } else { clk_set_parent(mali_parent_clock, mpll_clock); clk_set_parent(mali_clock, mali_parent_clock); } if (clk_enable(mali_clock) < 0) { printk("~~~~~~~~ERROR: [%s] %d\n ",__func__,__LINE__); return MALI_FALSE; } clk_set_rate(mali_clock, rate); rate = clk_get_rate(mali_clock); if (bis_vpll) mali_gpu_clk = (int)(rate / mhz); else mali_gpu_clk = (int)((rate + 500000) / mhz); GPU_MHZ = mhz; MALI_DEBUG_PRINT(2,("= clk_get_rate: %d \n",mali_gpu_clk)); mali_clk_put(MALI_FALSE); _mali_osk_mutex_signal(mali_dvfs_lock); return MALI_TRUE; }