phys_size_t initdram(int board_type) { u32 dramsize = 0; /* * Check to see if the SDRAM has already been initialized * by a run control tool */ if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { u32 RC, temp; RC = (CONFIG_SYS_CLK / 1000000) >> 1; RC = (RC * 15) >> 4; /* Initialize DRAM Control Register: DCR */ mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); __asm__("nop"); mbar_writeLong(MCFSIM_DACR0, 0x00003224); __asm__("nop"); /* Initialize DMR0 */ dramsize = (CONFIG_SYS_SDRAM_SIZE << 20); temp = (dramsize - 1) & 0xFFFC0000; mbar_writeLong(MCFSIM_DMR0, temp | 1); __asm__("nop"); mbar_writeLong(MCFSIM_DACR0, 0x0000322c); mb(); __asm__("nop"); /* Write to this block to initiate precharge */ *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; mb(); __asm__("nop"); /* Set RE bit in DACR */ mbar_writeLong(MCFSIM_DACR0, mbar_readLong(MCFSIM_DACR0) | 0x8000); __asm__("nop"); /* Wait for at least 8 auto refresh cycles to occur */ udelay(500); /* Finish the configuration by issuing the MRS */ mbar_writeLong(MCFSIM_DACR0, mbar_readLong(MCFSIM_DACR0) | 0x0040); __asm__("nop"); *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; mb(); }
/* * Breath some life into the CPU... * * Set up the memory map, * initialize a bunch of registers, * initialize the UPM's */ void cpu_init_f(void) { /* * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins * which is their primary function. * ~Jeremy */ mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC); mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC); mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN); mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN); mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT); mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT); /* * dBug Compliance: * You can verify these values by using dBug's 'ird' * (Internal Register Display) command * ~Jeremy * */ mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ mbar_writeByte(MCFSIM_SYPCR, 0x00); mbar_writeByte(MCFSIM_SWIVR, 0x0f); mbar_writeByte(MCFSIM_SWSR, 0x00); mbar_writeLong(MCFSIM_IMR, 0xfffffbff); mbar_writeByte(MCFSIM_SWDICR, 0x00); mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); mbar_writeByte(MCFSIM_I2CICR, 0x00); mbar_writeByte(MCFSIM_UART1ICR, 0x00); mbar_writeByte(MCFSIM_UART2ICR, 0x00); mbar_writeByte(MCFSIM_ICR6, 0x00); mbar_writeByte(MCFSIM_ICR7, 0x00); mbar_writeByte(MCFSIM_ICR8, 0x00); mbar_writeByte(MCFSIM_ICR9, 0x00); mbar_writeByte(MCFSIM_QSPIICR, 0x00); mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ mbar2_writeByte(MCFSIM_SPURVEC, 0x00); mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ /* Setup interrupt priorities for gpio7 */ /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */ /* IDE Config registers */ mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000); /* FlexBus Chipselect */ init_fbcs(); /* enable instruction cache now */ icache_enable(); }
void cpu_init_f(void) { #ifndef CONFIG_WATCHDOG /* Disable the watchdog if we aren't using it */ mbar_writeShort(MCF_WTM_WCR, 0); #endif /* FlexBus Chipselect */ init_fbcs(); #ifdef CONFIG_SYS_MCF_SYNCR /* Set clockspeed according to board header file */ mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR); #else /* Set clockspeed to 100MHz */ mbar_writeLong(MCF_FMPLL_SYNCR, MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0)); #endif while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ; }
void timer_init (void) { volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2); timestamp = 0; /* Set up TIMER 2 as clock */ timerp->timer_tmr = MCFTIMER_TMR_DISABLE; /* initialize and enable timer 2 interrupt */ irq_install_handler (31, mcf_timer_interrupt, 0); mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); mbar_writeByte(MCFSIM_TIMER2ICR, MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3); timerp->timer_tcn = 0; timerp->timer_trr = 1000; /* Interrupt every ms */ /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */ timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE; }
void dtimer_intr_setup(void) { mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI); }
/* * Breath some life into the CPU... * * Set up the memory map, * initialize a bunch of registers, * initialize the UPM's */ void cpu_init_f (void) { #ifndef CFG_PLL_BYPASS /* * Setup the PLL to run at the specified speed * */ volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); unsigned long pllcr; #ifdef CFG_FAST_CLK pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ #else pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ #endif cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ pllcr ^= 0x00000001; /* Set pll bypass to 1 */ mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ udelay(0x20); /* Wait for a lock ... */ #endif /* #ifndef CFG_PLL_BYPASS */ /* * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins * which is their primary function. * ~Jeremy */ mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC); mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC); mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN); mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN); mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT); mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT); /* * dBug Compliance: * You can verify these values by using dBug's 'ird' * (Internal Register Display) command * ~Jeremy * */ mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ mbar_writeByte(MCFSIM_SYPCR, 0x00); mbar_writeByte(MCFSIM_SWIVR, 0x0f); mbar_writeByte(MCFSIM_SWSR, 0x00); mbar_writeLong(MCFSIM_IMR, 0xfffffbff); mbar_writeByte(MCFSIM_SWDICR, 0x00); mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); mbar_writeByte(MCFSIM_I2CICR, 0x00); mbar_writeByte(MCFSIM_UART1ICR, 0x00); mbar_writeByte(MCFSIM_UART2ICR, 0x00); mbar_writeByte(MCFSIM_ICR6, 0x00); mbar_writeByte(MCFSIM_ICR7, 0x00); mbar_writeByte(MCFSIM_ICR8, 0x00); mbar_writeByte(MCFSIM_ICR9, 0x00); mbar_writeByte(MCFSIM_QSPIICR, 0x00); mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ mbar2_writeByte(MCFSIM_SPURVEC, 0x00); mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ /* Setup interrupt priorities for gpio7 */ /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */ /* IDE Config registers */ mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000); /* * Setup chip selects... */ mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1); mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1); mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1); mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0); mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0); mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0); /* enable instruction cache now */ icache_enable(); }
/* Function: deshabilitar_interrupciones Deshabilita todas las interrupciones de registro de configuracion ICR1. */ void deshabilitar_interrupciones(void) { mbar_writeLong(MCFSIM_ICR1, DESHABILITAR_INTERRUPCIONES); }
//------------------------------------------------------------------------------ // void setICR1(void) // // Descripción: Actualiza el vector ICR1 a 0x8888CB88, donde se marcan como no // pendientes las interrupciones TIMER0 TIMER1 y se establecen // sus prioridades como 4 y 3 respectivamente. // Fijamos mayor prioridad al TIMER 0 para que podamos emplear el // DAC respetando la temporización. // // Argumentos de Entrada: VOID // Argumentos de Salida: VOID // // Autores: Equipo docente de SDII //------------------------------------------------------------------------------ void ICR1_set(void) { mbar_writeLong(MCFSIM_ICR1, 0x8888C888); }