static void omap2_mcspi_save_ctx(struct omap2_mcspi *mcspi)
{
struct spi_master *spi_cntrl;
spi_cntrl = mcspi->master;
/* McSPI : context save */
mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl = mcspi_read_reg(spi_cntrl,
OMAP2_MCSPI_MODULCTRL);
mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig = mcspi_read_reg(spi_cntrl,
OMAP2_MCSPI_SYSCONFIG);
mcspi_ctx[spi_cntrl->bus_num - 1].chconf0 = mcspi_read_reg(spi_cntrl,
OMAP2_MCSPI_CHCONF0);
if (spi_cntrl->bus_num != 4)
mcspi_ctx[spi_cntrl->bus_num - 1].chconf1 =
mcspi_read_reg(spi_cntrl, OMAP2_MCSPI_CHCONF0 + 0x14);
}
static void omap2_mcspi_set_slave_mode(struct spi_master *master)
{
u32 l;
l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 1);
mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
}
static irqreturn_t mcspi_isr(int irq, void *data)
{
struct omap2_mcspi *mcspi;
u32 irqstatus;
mcspi = data;
/* Save and clear the status register to ack the IRQ */
irqstatus = mcspi_read_reg(mcspi->master,
OMAP2_MCSPI_IRQSTATUS);
irqstatus &= mcspi_read_reg(mcspi->master,
OMAP2_MCSPI_IRQENABLE);
mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, irqstatus);
mcspi->irq_status = irqstatus;
irqstatus = mcspi_read_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS);
complete(&mcspi->irq_completion);
return IRQ_HANDLED;
}
static void omap2_mcspi_set_master_mode(struct spi_device *spi, int single_channel)
{
u32 l;
/* Need reset when switching from slave mode */
l = mcspi_read_reg(spi->master, OMAP2_MCSPI_MODULCTRL);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, single_channel);
mcspi_write_reg(spi->master, OMAP2_MCSPI_MODULCTRL, l);
}
static void omap2_mcspi_set_master_mode(struct spi_master *master)
{
u32 l;
/* setup when switching from (reset default) slave mode
* to single-channel master mode
*/
l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
}
static void omap_mcspi_wakeup_enable(struct spi_master *spi_cntrl, int level)
{
if (level == OMAP2_MCSPI_SYS_CON_LVL_1)
mcspi_write_wkup_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
(mcspi_read_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG) |
OMAP2_MCSPI_SYSCFG_WKUP | OMAP2_MCSPI_SYSCFG_IDL |
OMAP2_MCSPI_SYSCFG_CLK |
OMAP2_MCSPI_SYSCONFIG_AUTOIDLE));
if (level == OMAP2_MCSPI_SYS_CON_LVL_2)
mcspi_write_wkup_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
(mcspi_read_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG) |
OMAP2_MCSPI_SYSCFG_WKUP | OMAP2_MCSPI_SYSCFG_IDL |
OMAP2_MCSPI_SYSCONFIG_AUTOIDLE));
mcspi_write_wkup_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
OMAP2_MCSPI_WAKEUP_EN);
/* enable wakeup interrupt*/
mcspi_write_wkup_reg(spi_cntrl, OMAP2_MCSPI_IRQENABLE,
(mcspi_read_reg(spi_cntrl,
OMAP2_MCSPI_IRQENABLE) | OMAP2_MCSPI_IRQ_WKS));
}
static int omap2_mcspi_set_rxfifo(const struct spi_device *spi, int buf_size,
int wl_bytes, int enable)
{
u32 l, rw, s, xfer_ael;
unsigned short revert = 0;
struct spi_master *master = spi->master;
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
u32 wcnt = buf_size/wl_bytes;
l = mcspi_cached_chconf0(spi);
s = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
/* Read settings for TX FIFO */
xfer_ael = mcspi_read_reg(master, OMAP2_MCSPI_XFERLEVEL) & 0xff;
if (enable == 1) {
/* Channel needs to be disabled and enabled
* for FIFO setting to take affect
*/
if (s & OMAP2_MCSPI_CHCTRL_EN) {
omap2_mcspi_set_enable(spi, 0);
revert = 1;
}
if (buf_size < mcspi->fifo_depth)
mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL,
((wcnt << 16) |
(buf_size - 1) << 8) |
xfer_ael);
else
mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL,
((wcnt << 16) |
(mcspi->fifo_depth - 1) << 8) |
xfer_ael);
} else {
/* Reset register value for disable case */
mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xfer_ael);
}
rw = OMAP2_MCSPI_CHCONF_FFER;
MOD_REG_BIT(l, rw, enable);
mcspi_write_chconf0(spi, l);
if (revert)
omap2_mcspi_set_enable(spi, 1);
return 0;
}
// LGE_UPDATE_S [email protected] [EBS] For DMA FIFO static int omap2_mcspi_dump_regs(struct spi_device *spi) { struct spi_master *master = spi->master; printk("OMAP2_MCSPI_REVISION 0x%08X\n",mcspi_read_reg(master, OMAP2_MCSPI_REVISION)); printk("OMAP2_MCSPI_SYSCONFIG 0x%08X\n",mcspi_read_reg(master, OMAP2_MCSPI_SYSCONFIG)); printk("OMAP2_MCSPI_SYSSTATUS 0x%08X\n",mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS)); printk("OMAP2_MCSPI_IRQSTATUS 0x%08X\n",mcspi_read_reg(master, OMAP2_MCSPI_IRQSTATUS)); printk("OMAP2_MCSPI_IRQENABLE 0x%08X\n",mcspi_read_reg(master, OMAP2_MCSPI_IRQENABLE)); printk("OMAP2_MCSPI_WAKEUPENABLE 0x%08X\n",mcspi_read_reg(master, OMAP2_MCSPI_WAKEUPENABLE)); printk("OMAP2_MCSPI_SYST 0x%08X\n",mcspi_read_reg(master, OMAP2_MCSPI_SYST)); printk("OMAP2_MCSPI_MODULCTRL 0x%08X\n",mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL)); printk("OMAP2_MCSPI_XFERLEVEL 0x%08X\n",mcspi_read_reg(master, OMAP2_MCSPI_XFERLEVEL)); printk("OMAP2_MCSPI_CHCONF0 0x%08X\n",mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0)); printk("OMAP2_MCSPI_CHSTAT0 0x%08X\n",mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)); printk("OMAP2_MCSPI_CHCTRL0 0x%08X\n",mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0)); printk("OMAP2_MCSPI_TX0 0x%08X\n",mcspi_read_cs_reg(spi, OMAP2_MCSPI_TX0)); printk("OMAP2_MCSPI_RX0 0x%08X\n",mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0)); return 0; }
static void omap2_mcspi_set_master_mode(struct spi_master *master)
{
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
struct omap2_mcspi_regs *ctx = &mcspi->ctx;
u32 l;
/*
* Setup when switching from (reset default) slave mode
* to single-channel master mode
*/
l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
ctx->modulctrl = l;
}
static void omap2_mcspi_set_master_mode(struct spi_master *master)
{
u32 l;
/* setup when switching from (reset default) slave mode
* to single-channel master mode
*/
l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
#ifdef CONFIG_SPI_SW_CS
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
#else
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 0);
#endif
mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
}
static void omap2_mcspi_set_master_mode(struct spi_master *master)
{
u32 l;
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
/* setup when switching from (reset default) slave mode
* to single-channel master mode based on config value
*/
l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
if (mcspi->force_cs_mode)
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
}
static void omap2_mcspi_set_mode(struct spi_master *master)
{
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
struct omap2_mcspi_regs *ctx = &mcspi->ctx;
u32 l;
/*
* Choose master or slave mode
*/
l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
l &= ~(OMAP2_MCSPI_MODULCTRL_STEST);
if (spi_controller_is_slave(master)) {
l |= (OMAP2_MCSPI_MODULCTRL_MS);
} else {
l &= ~(OMAP2_MCSPI_MODULCTRL_MS);
l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
}
mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
ctx->modulctrl = l;
}