//SW2-6-MM-JH-Backlight_PWM-01+ static void mddi_toshiba_fwvga_lcd_set_backlight_pwm(struct msm_fb_data_type *mfd, struct backlight_regs *bl_regs) { printk(KERN_INFO "MDDI: set backlight pwm = %d\n", bl_regs->pwm); mddi_queue_register_write( 0x00C0, 0x0001, FALSE, 0); // CMD2 Page CTRL: Page 1 mddi_queue_register_write( 0x22C0, 0x0004, FALSE, 0); // ABC CTRL11: PWMDIV; PWMDIV[7:0] = 4; PWM Frequency = 19531.3 mddi_queue_register_write( 0x5300, 0x0036, FALSE, 0); // WRCTRLD: Write CTRL Display; BCTRL=1, A=1,BL=1, DB=1 mddi_queue_register_write( 0x71C0, bl_regs->pwm , FALSE, 0); // CABC_FORCE mddi_queue_register_write( 0x18C0, 0x0005, FALSE, 0); // ABC_CTRL1(FORCE_LABC, LENONR, FORCE_CABC_PWM) }
static int __init mddi_nt35560_probe(struct platform_device *pdev) { uint32 id = 0; msm_fb_add_device(pdev); mddi_queue_register_read(0x1F80, &id, TRUE, 0); printk(KERN_INFO "%s user id: 0x%x\n", __func__,id); //Turn on Vsync on 700th line mddi_queue_register_write(0x4400, 0x02, FALSE, 0); mddi_queue_register_write(0x4401, 0xBC, FALSE, 0); mddi_queue_register_write(0x3500, 0x00, FALSE, 0); return 0; }
static void mddi_toshiba_fwvga_lcd_shutdown(struct platform_device *dev) { printk(KERN_INFO "MDDI: mddi_toshiba_fwvga_lcd_shutdown\n"); mddi_queue_register_write( 0x2800, 0x0000, FALSE, 0); // SET_DISPLAY_OFF mddi_queue_register_write( 0x1000, 0x0000, FALSE, 0); // ENTER_SLEEP_MODE mddi_wait(70); // LCM_RESET -> Low gpio_set_value(GPIO_LCM_RESET, 0); // PM8058_LVS1_V1P8 vreg_disable(vreg_lvsw1); // PM8058_L15_V2P85 vreg_disable(vreg_gp6); }
static int nt35582_lcd_off(struct platform_device *pdev) { int ret; /*enter sleep mode*/ ret = mddi_queue_register_write(0x1000,0,TRUE,0); mdelay(50); MDDI_LCD_DEBUG("%s: nt35582_lcd enter sleep mode ,off_ret=%d\n",__func__,ret); return ret; }
static ssize_t nov_data_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { unsigned val; sscanf(buf, "%u", &val); mddi_queue_register_write(addr, val, 0, 0); return count; }
static ssize_t nov_t2_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { unsigned val; sscanf(buf, "%u", &val); mddi_queue_register_write(0xb101, val & 0xff, 0, 0); mddi_queue_register_write(0xb102, (val >> 8) &0xff, 0, 0); return count; }
static void mddi_tpo_nv_esd_poll(void* arg) { #ifdef MDDI_TPO_NV_ESD_DEBUG uint32_t val; #endif struct platform_device *pdev = (struct platform_device *)arg; msm_fb_down(pdev); #ifdef MDDI_TPO_NV_ESD_DEBUG printk(KERN_ERR "TPO NV - ESD register check START\n"); mddi_queue_register_write(ENTRYMODE2 ,0x00C4, 0, 0); mddi_wait(20); for (i = 0;; i++) { if (disp_init[i].reg == TABLE_END) { break; } else if (disp_init[i].reg != MDDI_SLEEP_CMD) { mddi_queue_register_read(disp_init[i].reg, &val, 1, 0); if (disp_init[i].val != val) { printk(KERN_ERR "TPO NV reg 0x%X should be 0x%X, found 0x%X\n", disp_init[i].reg, disp_init[i].val, val); } } } mddi_queue_register_write(ENTRYMODE2 ,0x00C5, 0, 0); mddi_wait(30); printk(KERN_ERR "TPO NV - ESD register check END\n"); #endif /* MDDI_TPO_NV_ESD_DEBUG */ if (disp_esd_recovery) { xmit_panel_seq(disp_esd_recovery); } msm_fb_up(pdev); }
static int mddi_nt35560_lcd_off(struct platform_device *pdev) { printk("%s \n",__func__); gpio_set_value(GPIO_LCD_RESET, 0); mddi_queue_register_write(0x3400, 0x00, FALSE, 0); //Display off mddi_queue_register_write(0x2800, 0x00, FALSE, 0); //Sleep mddi_queue_register_write(0x1000, 0x00, FALSE, 0); //Deep sleep mddi_queue_register_write(0x4F00, 0x01, FALSE, 0); //Remux the reset pin to input pinmux_config("LCD_RESET", PINMUX_CONFIG_SLEEP); pinmux_config("LCD_TE", PINMUX_CONFIG_SLEEP); return 0; }
static boolean serigo(uint32 reg, uint32 len, const char *params, boolean wait) { uint32 rv; uint32 data_list[20]; uint i; for (i = 0; i < len; ++i) data_list[i] = (u32)params[i] & 0xFF; if (len > 0) rv = mddi_host_register_multiwrite(reg, len, data_list, wait, \ NULL, MDDI_HOST_PRIM); else rv = mddi_queue_register_write(reg, 0, TRUE, 0); mddi_wait(10); return rv; }
/*============================================================================= LOCAL FUNCTIONS =============================================================================*/ static void xmit_panel_seq(struct init_table const *init_table) { unsigned n; for (n = 0;; n++) { if (init_table[n].reg == TABLE_END) { break; } else if (init_table[n].reg == MDDI_SLEEP_CMD) { mddi_wait(init_table[n].val); } else { mddi_queue_register_write(init_table[n].reg, init_table[n].val, 0, 0); } } }
static int mddi_nt35560_lcd_on(struct platform_device *pdev) { printk("%s \n",__func__); //Remux the reset pin to output pinmux_config("LCD_RESET", PINMUX_CONFIG_ACTIVE); pinmux_config("LCD_TE", PINMUX_CONFIG_ACTIVE); //Reset (stay low for more than 3 ms) gpio_set_value(GPIO_LCD_RESET, 0); msleep(20); gpio_set_value(GPIO_LCD_RESET, 1); msleep(20); //Sleep out mddi_queue_register_write(0x1100, 0x00, FALSE, 0); /* * Spec sugggests 10ms or more. * Reality indicates 100ms provides a good buffer * for internal MTP programming. */ msleep(100); //Display on mddi_queue_register_write(0x2900, 0x00, FALSE, 0); //Turn on Vsync on 700th line mddi_queue_register_write(0x4400, 0x02, FALSE, 0); mddi_queue_register_write(0x4401, 0xBC, FALSE, 0); mddi_queue_register_write(0x3500, 0x00, FALSE, 0); if (mddi_nt35560_pdata && mddi_nt35560_pdata->flip) { uint32_t address_mode = 0; if (mddi_nt35560_pdata->flip & MSM_PANEL_CONFIG_FLIP_VERTICAL) address_mode |= 0x80; if (mddi_nt35560_pdata->flip & MSM_PANEL_CONFIG_FLIP_HORIZONTAL) address_mode |= 0x40; mddi_queue_register_write(0x3600, address_mode, FALSE, 0); } return 0; }
void panel_init(struct init_table *init_table) { unsigned int n; printk(KERN_INFO "MDDI: panel_init()\n"); n = 0; while (init_table[n].reg != 0 || init_table[n].val != 0) { if (init_table[n].reg != 0) { // printk(KERN_INFO "write Address(0x%08x), Data(0x%08x)\n", init_table[n].reg, init_table[n].val); mddi_queue_register_write(init_table[n].reg, init_table[n].val, FALSE, 0); } else { printk(KERN_INFO "mdelay %d\n", init_table[n].val); mddi_wait(init_table[n].val); printk(KERN_INFO "mdelay %d done\n", init_table[n].val); } n++; } printk(KERN_INFO "MDDI: panel_init() done\n"); }
static void mddi_toshiba_fwvga_lcd_set_backlight(struct msm_fb_data_type *mfd) { printk(KERN_INFO "MDDI: set backlight level = %d\n", mfd->bl_level); /*Div2-SW6-SC-Panel_Init_timing-00*{*/ if (!bLCD_BKL_ON_State) { mddi_queue_register_write( 0x2900, 0x0000, FALSE, 0); // SET_DISPLAY_ON bLCD_BKL_ON_State = 1; } else if (!mfd->bl_level) { mddi_queue_register_write( 0x2800, 0x0000, FALSE, 0); // SET_DISPLAY_OFF bLCD_BKL_ON_State = 0; } /*Div2-SW6-SC-Panel_Init_timing-00*}*/ mddi_queue_register_write( 0x00C0, 0x0001, FALSE, 0); // CMD2 Page CTRL: Page 1 mddi_queue_register_write( 0x22C0, 0x0004, FALSE, 0); // ABC CTRL11: PWMDIV; PWMDIV[7:0] = 4; PWM Frequency = 19531.3 mddi_queue_register_write( 0x5300, 0x0036, FALSE, 0); // WRCTRLD: Write CTRL Display; BCTRL=1, A=1,BL=1, DB=1 //SW2-6-MM-JH-PWM-00+ mddi_queue_register_write( 0x71C0, PWM[mfd->bl_level], FALSE, 0); // CABC_FORCE //SW2-6-MM-JH-PWM-00- mddi_queue_register_write( 0x18C0, 0x0005, FALSE, 0); // ABC_CTRL1(FORCE_LABC, LENONR, FORCE_CABC_PWM) }
int process_mddi_table(struct sequence *table, size_t count, lcd_panel_type lcd_panel) { unsigned int i; uint32 reg = 0; uint32 value = 0; uint32 time = 0; int ret = 0; int clk_on = 0; for (i = 0; i < count; i++) { reg = table[i].reg; value = table[i].value; time = table[i].time; switch(lcd_panel) { case LCD_NT35582_BYD_WVGA: case LCD_NT35582_TRULY_WVGA: case LCD_NT35510_ALPHA_SI_WVGA: case LCD_NT35560_TOSHIBA_FWVGA: case LCD_NT35510_ALPHA_SI_WVGA_TYPE2: down(&mdp_pipe_ctrl_mutex); clk_on = pmdh_clk_func(2); pmdh_clk_func(1); /* MDDI port to write the reg and value */ ret = mddi_queue_register_write(reg,value,TRUE,0); if (clk_on == 0) { pmdh_clk_func(0); } up(&mdp_pipe_ctrl_mutex); break; case MDDI_RSP61408_CHIMEI_WVGA: case MDDI_RSP61408_BYD_WVGA: case MDDI_HX8369A_TIANMA_WVGA: case MDDI_HX8357C_CHIMEI_HVGA: case MDDI_HX8357C_TIANMA_HVGA: case MDDI_HX8357C_CHIMEI_IPS_HVGA: down(&mdp_pipe_ctrl_mutex); clk_on = pmdh_clk_func(2); pmdh_clk_func(1); ret = mddi_multi_register_write(reg,value); if (clk_on == 0) { pmdh_clk_func(0); } up(&mdp_pipe_ctrl_mutex); break; default: break; } if (time != 0) { LCD_MDELAY(time); } } return ret; }
void bkl_write_reg(unsigned int addr, unsigned int data) { MSG("Write 0x%04X = 0x%04X",addr,data); mddi_queue_register_write(addr, data, FALSE, 0); mdelay(5); };