static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd) { int phy_id = efx->mii.phy_id; u32 reg; if (efx_phy_mode_disabled(efx->phy_mode)) return false; else if (efx->loopback_mode == LOOPBACK_GPHY) return true; else if (efx->loopback_mode) return mdio_clause45_links_ok(efx, MDIO_MMDREG_DEVS_PMAPMD | MDIO_MMDREG_DEVS_PHYXS); /* We must use the same definition of link state as LASI, * otherwise we can miss a link state transition */ if (ecmd->speed == 10000) { reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS, PCS_10GBASET_STAT1); return reg & (1 << PCS_10GBASET_BLKLK_LBN); } else { reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT, C22EXT_STATUS_REG); return reg & (1 << C22EXT_STATUS_LINK_LBN); } }
/* Poll PHY for interrupt */ static void tenxpress_phy_poll(struct efx_nic *efx) { struct tenxpress_phy_data *phy_data = efx->phy_data; bool change = false; if (efx->phy_type == PHY_TYPE_SFX7101) { bool link_ok = sfx7101_link_ok(efx); if (link_ok != efx->link_up) { change = true; } else { unsigned int link_fc = mdio_clause45_get_pause(efx); if (link_fc != efx->link_fc) change = true; } sfx7101_check_bad_lp(efx, link_ok); } else if (efx->loopback_mode) { bool link_ok = sft9001_link_ok(efx, NULL); if (link_ok != efx->link_up) change = true; } else { u32 status = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, PMA_PMD_LASI_STATUS); if (status & (1 << PMA_PMD_LS_ALARM_LBN)) change = true; } if (change) falcon_sim_phy_event(efx); if (phy_data->phy_mode != PHY_MODE_NORMAL) return; }
/* Perform a "special software reset" on the PHY. The caller is * responsible for saving and restoring the PHY hardware registers * properly, and masking/unmasking LASI */ static int tenxpress_special_reset(struct efx_nic *efx) { int rc, reg; /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so * a special software reset can glitch the XGMAC sufficiently for stats * requests to fail. */ efx_stats_disable(efx); /* Initiate reset */ reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); reg |= (1 << PMA_PMD_EXT_SSR_LBN); mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); mdelay(200); /* Wait for the blocks to come out of reset */ rc = mdio_clause45_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS); if (rc < 0) goto out; /* Try and reconfigure the device */ rc = tenxpress_init(efx); if (rc < 0) goto out; /* Wait for the XGXS state machine to churn */ mdelay(10); out: efx_stats_enable(efx); return rc; }
static int tenxpress_phy_init(struct efx_nic *efx) { struct tenxpress_phy_data *phy_data; int rc = 0; phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL); if (!phy_data) return -ENOMEM; efx->phy_data = phy_data; phy_data->phy_mode = efx->phy_mode; if (!(efx->phy_mode & PHY_MODE_SPECIAL)) { if (efx->phy_type == PHY_TYPE_SFT9001A) { int reg; reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); reg |= (1 << PMA_PMD_EXT_SSR_LBN); mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); mdelay(200); } rc = mdio_clause45_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS); if (rc < 0) goto fail; rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0); if (rc < 0) goto fail; } rc = tenxpress_init(efx); if (rc < 0) goto fail; mdio_clause45_set_pause(efx); if (efx->phy_type == PHY_TYPE_SFT9001B) { rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_short_reach); if (rc) goto fail; } schedule_timeout_uninterruptible(HZ / 5); /* 200ms */ /* Let XGXS and SerDes out of reset */ falcon_reset_xaui(efx); return 0; fail: kfree(efx->phy_data); efx->phy_data = NULL; return rc; }
static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok) { struct tenxpress_phy_data *pd = efx->phy_data; int phy_id = efx->mii.phy_id; bool bad_lp; int reg; if (link_ok) { bad_lp = false; } else { /* Check that AN has started but not completed. */ reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, MDIO_AN_STATUS); if (!(reg & (1 << MDIO_AN_STATUS_LP_AN_CAP_LBN))) return; /* LP status is unknown */ bad_lp = !(reg & (1 << MDIO_AN_STATUS_AN_DONE_LBN)); if (bad_lp) pd->bad_lp_tries++; } /* Nothing to do if all is well and was previously so. */ if (!pd->bad_lp_tries) return; /* Use the RX (red) LED as an error indicator once we've seen AN * failure several times in a row, and also log a message. */ if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) { reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG); reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN); if (!bad_lp) { reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN; } else { reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN; EFX_ERR(efx, "appears to be plugged into a port" " that is not 10GBASE-T capable. The PHY" " supports 10GBASE-T ONLY, so no link can" " be established\n"); } mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg); pd->bad_lp_tries = bad_lp; } }
static ssize_t show_phy_short_reach(struct device *dev, struct device_attribute *attr, char *buf) { struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); int reg; reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, MDIO_PMAPMD_10GBT_TXPWR); return sprintf(buf, "%d\n", !!(reg & (1 << MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN))); }
static void tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) { int phy_id = efx->mii.phy_id; u32 adv = 0, lpa = 0; int reg; if (efx->phy_type != PHY_TYPE_SFX7101) { reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL); if (reg & (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN)) adv |= ADVERTISED_1000baseT_Full; reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT, C22EXT_MSTSLV_STATUS); if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN)) lpa |= ADVERTISED_1000baseT_Half; if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN)) lpa |= ADVERTISED_1000baseT_Full; } reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL); if (reg & (1 << MDIO_AN_10GBT_CTRL_ADV_10G_LBN)) adv |= ADVERTISED_10000baseT_Full; reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, MDIO_AN_10GBT_STATUS); if (reg & (1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN)) lpa |= ADVERTISED_10000baseT_Full; mdio_clause45_get_settings_ext(efx, ecmd, adv, lpa); if (efx->phy_type != PHY_TYPE_SFX7101) ecmd->supported |= (SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full); /* In loopback, the PHY automatically brings up the correct interface, * but doesn't advertise the correct speed. So override it */ if (efx->loopback_mode == LOOPBACK_GPHY) ecmd->speed = SPEED_1000; else if (LOOPBACK_MASK(efx) & efx->phy_op->loopbacks) ecmd->speed = SPEED_10000; }
int sft9001_wait_boot(struct efx_nic *efx) { unsigned long timeout = jiffies + HZ + 1; int boot_stat; for (;;) { boot_stat = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PCS, PCS_BOOT_STATUS_REG); if (boot_stat >= 0) { EFX_LOG(efx, "PHY boot status = %#x\n", boot_stat); switch (boot_stat & ((1 << PCS_BOOT_FATAL_ERROR_LBN) | (3 << PCS_BOOT_PROGRESS_LBN) | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) | (1 << PCS_BOOT_CODE_STARTED_LBN))) { case ((1 << PCS_BOOT_FATAL_ERROR_LBN) | (PCS_BOOT_PROGRESS_CHECKSUM << PCS_BOOT_PROGRESS_LBN)): case ((1 << PCS_BOOT_FATAL_ERROR_LBN) | (PCS_BOOT_PROGRESS_INIT << PCS_BOOT_PROGRESS_LBN) | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)): return -EINVAL; case ((PCS_BOOT_PROGRESS_WAIT_MDIO << PCS_BOOT_PROGRESS_LBN) | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)): return (efx->phy_mode & PHY_MODE_SPECIAL) ? 0 : -EIO; case ((PCS_BOOT_PROGRESS_JUMP << PCS_BOOT_PROGRESS_LBN) | (1 << PCS_BOOT_CODE_STARTED_LBN)): case ((PCS_BOOT_PROGRESS_JUMP << PCS_BOOT_PROGRESS_LBN) | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) | (1 << PCS_BOOT_CODE_STARTED_LBN)): return (efx->phy_mode & PHY_MODE_SPECIAL) ? -EIO : 0; default: if (boot_stat & (1 << PCS_BOOT_FATAL_ERROR_LBN)) return -EIO; break; } } if (time_after_eq(jiffies, timeout)) return -ETIMEDOUT; msleep(50); } }
static int tenxpress_init(struct efx_nic *efx) { int phy_id = efx->mii.phy_id; int reg; if (efx->phy_type == PHY_TYPE_SFX7101) { /* Enable 312.5 MHz clock */ mdio_clause45_write(efx, phy_id, MDIO_MMD_PCS, PCS_TEST_SELECT_REG, 1 << CLK312_EN_LBN); } else { /* Enable 312.5 MHz clock and GMII */ reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) | (1 << PMA_PMD_EXT_CLK_OUT_LBN) | (1 << PMA_PMD_EXT_CLK312_LBN) | (1 << PMA_PMD_EXT_ROBUST_LBN)); mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT, GPHY_XCONTROL_REG, GPHY_ISOLATE_LBN, false); } /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */ if (efx->phy_type == PHY_TYPE_SFX7101) { mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG, PMA_PMA_LED_ACTIVITY_LBN, true); mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, PMA_PMD_LED_DEFAULT); } return 0; }
/* Check that the C166 has booted successfully */ static int tenxpress_phy_check(struct efx_nic *efx) { int phy_id = efx->mii.phy_id; int count = PCS_BOOT_MAX_DELAY / PCS_BOOT_POLL_DELAY; int boot_stat; /* Wait for the boot to complete (or not) */ while (count) { boot_stat = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS, PCS_BOOT_STATUS_REG); if (boot_stat & (1 << PCS_BOOT_COMPLETE_LBN)) break; count--; udelay(PCS_BOOT_POLL_DELAY); } if (!count) { EFX_ERR(efx, "%s: PHY boot timed out. Last status " "%x\n", __func__, (boot_stat >> PCS_BOOT_PROGRESS_LBN) & ((1 << PCS_BOOT_PROGRESS_WIDTH) - 1)); return -ETIMEDOUT; }
static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags) { struct ethtool_cmd ecmd; int phy_id = efx->mii.phy_id; int rc = 0, rc2, i, ctrl_reg, res_reg; if (flags & ETH_TEST_FL_OFFLINE) efx->phy_op->get_settings(efx, &ecmd); /* Initialise cable diagnostic results to unknown failure */ for (i = 1; i < 9; ++i) results[i] = -1; /* Run cable diagnostics; wait up to 5 seconds for them to complete. * A cable fault is not a self-test failure, but a timeout is. */ ctrl_reg = ((1 << CDIAG_CTRL_IMMED_LBN) | (CDIAG_CTRL_LEN_METRES << CDIAG_CTRL_LEN_UNIT_LBN)); if (flags & ETH_TEST_FL_OFFLINE) { /* Break the link in order to run full diagnostics. We * must reset the PHY to resume normal service. */ ctrl_reg |= (1 << CDIAG_CTRL_BRK_LINK_LBN); } mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG, ctrl_reg); i = 0; while (mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG) & (1 << CDIAG_CTRL_IN_PROG_LBN)) { if (++i == 50) { rc = -ETIMEDOUT; goto out; } msleep(100); } res_reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_RES_REG); for (i = 0; i < 4; i++) { int pair_res = (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH)) & ((1 << CDIAG_RES_WIDTH) - 1); int len_reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_LEN_REG + i); if (pair_res == CDIAG_RES_OK) results[1 + i] = 1; else if (pair_res == CDIAG_RES_INVALID) results[1 + i] = -1; else results[1 + i] = -pair_res; if (pair_res != CDIAG_RES_INVALID && pair_res != CDIAG_RES_OPEN && len_reg != 0xffff) results[5 + i] = len_reg; } out: if (flags & ETH_TEST_FL_OFFLINE) { /* Reset, running the BIST and then resuming normal service. */ rc2 = tenxpress_special_reset(efx); results[0] = rc2 ? -1 : 1; if (!rc) rc = rc2; rc2 = efx->phy_op->set_settings(efx, &ecmd); if (!rc) rc = rc2; } return rc; }