void mdp4_overlay_dsi_video_start(void)
{
if (!dsi_video_enabled) {
/* enable DSI block */
mdp4_iommu_attach();
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
dsi_video_enabled = 1;
xlog(__func__, 0, 0, 0, 0, 0);
}
}
void mdp4_overlay_dsi_video_start(void)
{
if (!dsi_video_enabled) {
/* enable DSI block */
mdp4_iommu_attach();
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
dsi_video_enabled = 1;
}
}
void mdp4_overlay_lcdc_start(void)
{
if (!lcdc_enabled) {
/* enable LCDC block */
mdp4_iommu_attach();
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
MDP_OUTP(MDP_BASE + LCDC_BASE, 1);
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
lcdc_enabled = 1;
}
}
void mdp4_overlay_dtv_start(void)
{
if (!dtv_enabled) {
mdp4_iommu_attach();
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
/* enable DTV block */
MDP_OUTP(MDP_BASE + DTV_BASE, 1);
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
dtv_enabled = 1;
}
}
static void mdp4_overlay_dsi_video_start(void)
{
if (!dsi_video_enabled) {
/* enable DSI block */
/* OPPO 3013-06-06 Gousj modify for LCD Stuck*/
mdp4_iommu_attach();
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
/* OPPO 3013-06-06 Gousj modify end*/
dsi_video_enabled = 1;
}
}
void mdp4_overlay_lcdc_start(void)
{
if (!lcdc_enabled) {
/* enable LCDC block */
mdp4_iommu_attach();
#ifndef CONFIG_FB_MSM_LCDC_LGDISPLAY_WVGA_OLED //jeong.min.kim 2013-04-05
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
MDP_OUTP(MDP_BASE + LCDC_BASE, 1);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
#endif /* CONFIG_FB_MSM_LCDC_LGDISPLAY_WVGA_OLED */
lcdc_enabled = 1;
}
}
void mdp4_dsi_cmd_overlay_kickoff(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe)
{
unsigned long flag;
mdp4_iommu_attach();
/* change mdp clk */
mdp4_set_perf_level();
mipi_dsi_mdp_busy_wait(mfd);
mipi_dsi_cmd_mdp_start();
mdp4_overlay_dsi_state_set(ST_DSI_PLAYING);
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
spin_lock_irqsave(&mdp_spin_lock, flag);
outp32(MDP_INTR_CLEAR, INTR_DMA_P_DONE);
outp32(MDP_INTR_CLEAR, INTR_OVERLAY0_DONE);
mdp_intr_mask |= INTR_DMA_P_DONE;
if (dsi_pipe && dsi_pipe->ov_blt_addr) {
mdp_intr_mask |= INTR_OVERLAY0_DONE;
mfd->dma->busy = TRUE;
} else
mdp_intr_mask &= ~INTR_OVERLAY0_DONE;
mfd->dma->dmap_busy = TRUE;
outp32(MDP_INTR_ENABLE, mdp_intr_mask);
mdp_enable_irq(MDP_DMA2_TERM);
wmb();
spin_unlock_irqrestore(&mdp_spin_lock, flag);
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
wmb();
mdp4_stat.kickoff_ov0++;
dsi_pipe->ov_cnt++;
if (dsi_pipe && dsi_pipe->ov_blt_addr) {
wmb();
outpdw(MDP_BASE + 0x000c, 0x0);
mdp4_stat.kickoff_dmap++;
wmb();
dsi_pipe->dmap_cnt++;
dsi_pipe->blt_cnt++;
}
}
int mdp4_dsi_cmd_on(struct platform_device *pdev)
{
int ret = 0;
int cndx = 0;
struct msm_fb_data_type *mfd;
struct vsycn_ctrl *vctrl;
pr_debug("%s+: pid=%d\n", __func__, current->pid);
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
mfd->cont_splash_done = 1;
vctrl = &vsync_ctrl_db[cndx];
vctrl->mfd = mfd;
vctrl->dev = mfd->fbi->dev;
mdp_clk_ctrl(1);
mdp4_overlay_update_dsi_cmd(mfd);
mdp_clk_ctrl(0);
mdp4_iommu_attach();
atomic_set(&vctrl->suspend, 0);
if (!vctrl->sysfs_created) {
ret = sysfs_create_group(&vctrl->dev->kobj,
&vsync_fs_attr_group);
if (ret) {
pr_err("%s: sysfs group creation failed, ret=%d\n",
__func__, ret);
return ret;
}
kobject_uevent(&vctrl->dev->kobj, KOBJ_ADD);
pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
vctrl->sysfs_created = 1;
}
pr_debug("%s-:\n", __func__);
return ret;
}
int mdp4_dsi_cmd_on(struct platform_device *pdev)
{
int ret = 0;
int cndx = 0;
struct msm_fb_data_type *mfd;
struct vsycn_ctrl *vctrl;
pr_debug("%s+: pid=%d\n", __func__, current->pid);
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
mfd->cont_splash_done = 1;
mutex_lock(&mfd->dma->ov_mutex);
vctrl = &vsync_ctrl_db[cndx];
vctrl->mfd = mfd;
vctrl->dev = mfd->fbi->dev;
vctrl->vsync_enabled = 0;
if (!(mfd->cont_splash_done)) {
mfd->cont_splash_done = 1;
mipi_dsi_controller_cfg(0);
pr_debug("%s: Disabling DSI ctrl\n", __func__);
}
mdp_clk_ctrl(1);
mdp4_overlay_update_dsi_cmd(mfd);
mdp_clk_ctrl(0);
mdp4_iommu_attach();
atomic_set(&vctrl->suspend, 0);
mutex_unlock(&mfd->dma->ov_mutex);
pr_debug("%s-:\n", __func__);
return ret;
}
int mdp4_dsi_cmd_on(struct platform_device *pdev)
{
int ret = 0;
int cndx = 0;
struct msm_fb_data_type *mfd;
struct vsycn_ctrl *vctrl;
pr_debug("%s+: pid=%d\n", __func__, current->pid);
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
#ifdef CONFIG_F_SKYDISP_QCBUGFIX_CONTINUOUS_SPLASH_SCREEN // 20121217, kkcho, for sleep_current
if (!(mfd->cont_splash_done)) {
mfd->cont_splash_done = 1;
/* Clks are enabled in probe.
Disabling clocks now */
mdp_clk_ctrl(0);
}
#else
mfd->cont_splash_done = 1;
#endif
vctrl = &vsync_ctrl_db[cndx];
vctrl->mfd = mfd;
vctrl->dev = mfd->fbi->dev;
mdp_clk_ctrl(1);
mdp4_overlay_update_dsi_cmd(mfd);
mdp_clk_ctrl(0);
mdp4_iommu_attach();
atomic_set(&vctrl->suspend, 0);
pr_debug("%s-:\n", __func__);
return ret;
}
int mdp4_dsi_video_pipe_commit(int cndx, int wait)
{
int i, undx;
int mixer = 0;
struct vsycn_ctrl *vctrl;
struct vsync_update *vp;
struct mdp4_overlay_pipe *pipe;
struct mdp4_overlay_pipe *real_pipe;
unsigned long flags;
int cnt = 0;
vctrl = &vsync_ctrl_db[cndx];
mutex_lock(&vctrl->update_lock);
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
mutex_unlock(&vctrl->update_lock);
return 0;
}
mixer = pipe->mixer_num;
mdp_update_pm(vctrl->mfd, vctrl->vsync_time);
/*
* allow stage_commit without pipes queued
* (vp->update_cnt == 0) to unstage pipes after
* overlay_unset
*/
vctrl->update_ndx++;
vctrl->update_ndx &= 0x01;
vp->update_cnt = 0; /* reset */
if (vctrl->blt_free) {
vctrl->blt_free--;
if (vctrl->blt_free == 0)
mdp4_free_writeback_buf(vctrl->mfd, mixer);
}
mutex_unlock(&vctrl->update_lock);
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->ov_koff != vctrl->ov_done) {
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
pr_err("%s: Error, frame dropped %d %d\n", __func__,
vctrl->ov_koff, vctrl->ov_done);
return 0;
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (!vctrl->mfd->cont_splash_done)
mdp4_iommu_attach();
pipe = vp->plist;
for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {
if (pipe->pipe_used) {
cnt++;
real_pipe = mdp4_overlay_ndx2pipe(pipe->pipe_ndx);
if (real_pipe && real_pipe->pipe_used) {
/*
* commit pipes which are in pending queue
* and not be unset yet
*/
mdp4_overlay_vsync_commit(pipe);
}
}
}
mdp4_mixer_stage_commit(mixer);
/* start timing generator & mmu if they are not started yet */
mdp4_overlay_dsi_video_start();
/*
* there has possibility that pipe commit come very close to next vsync
* this may cause two consecutive pie_commits happen within same vsync
* period which casue iommu page fault when previous iommu buffer
* freed. Set ION_IOMMU_UNMAP_DELAYED flag at ion_map_iommu() to
* add delay unmap iommu buffer to fix this problem.
* Also ion_unmap_iommu() may take as long as 9 ms to free an ion buffer.
* therefore mdp4_overlay_iommu_unmap_freelist(mixer) should be called
* ater stage_commit() to ensure pipe_commit (up to stage_commit)
* is completed within vsync period.
*/
/* free previous committed iommu back to pool */
mdp4_overlay_iommu_unmap_freelist(mixer);
pipe = vp->plist;
for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {
if (pipe->pipe_used) {
/* free previous iommu to freelist
* which will be freed at next
* pipe_commit
*/
mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 0);
pipe->pipe_used = 0; /* clear */
}
}
pipe = vctrl->base_pipe;
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
mdp4_dsi_video_blt_ov_update(pipe);
pipe->ov_cnt++;
INIT_COMPLETION(vctrl->ov_comp);
vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);
mb();
vctrl->ov_koff++;
/* kickoff overlay engine */
mdp4_stat.kickoff_ov0++;
outpdw(MDP_BASE + 0x0004, 0);
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_stat.overlay_commit[pipe->mixer_num]++;
if (wait) {
mutex_unlock(&vctrl->mfd->dma->ov_mutex);
if (pipe->ov_blt_addr)
mdp4_dsi_video_wait4ov(0);
else
mdp4_dsi_video_wait4vsync(0);
mutex_lock(&vctrl->mfd->dma->ov_mutex);
}
return cnt;
}