Esempio n. 1
0
static void mdp4_dtv_do_blt(struct msm_fb_data_type *mfd, int enable)
{
	unsigned long flag;
	int change = 0;

	if (!mfd->ov1_wb_buf->phys_addr) {
		pr_debug("%s: no writeback buf assigned\n", __func__);
		return;
	}

	spin_lock_irqsave(&mdp_spin_lock, flag);
	if (enable && dtv_pipe->blt_addr == 0) {
		dtv_pipe->blt_addr = mfd->ov1_wb_buf->phys_addr;
		change++;
		dtv_pipe->ov_cnt = 0;
		dtv_pipe->dmae_cnt = 0;
	} else if (enable == 0 && dtv_pipe->blt_addr) {
		dtv_pipe->blt_addr = 0;
		change++;
	}
	pr_debug("%s: blt_addr=%x\n", __func__, (int)dtv_pipe->blt_addr);
	spin_unlock_irqrestore(&mdp_spin_lock, flag);

	if (!change)
		return;

	mdp4_overlay_dtv_wait4dmae(mfd);

	MDP_OUTP(MDP_BASE + DTV_BASE, 0);	/* stop dtv */
	msleep(20);
	mdp4_overlayproc_cfg(dtv_pipe);
	mdp4_overlay_dmae_xy(dtv_pipe);
	MDP_OUTP(MDP_BASE + DTV_BASE, 1);	/* start dtv */
}
Esempio n. 2
0
static void mdp4_dtv_do_blt(struct msm_fb_data_type *mfd, int enable)
{
	unsigned long flag;
	int change = 0;

	if (!mfd->ov1_wb_buf->write_addr) {
		pr_debug("%s: no writeback buf assigned\n", __func__);
		return;
	}

	if (!dtv_pipe) {
		pr_debug("%s: no mixer1 base layer pipe allocated!\n",
			 __func__);
		return;
	}

	spin_lock_irqsave(&mdp_spin_lock, flag);
	if (enable && dtv_pipe->ov_blt_addr == 0) {
		dtv_pipe->ov_blt_addr = mfd->ov1_wb_buf->write_addr;
		dtv_pipe->dma_blt_addr = mfd->ov1_wb_buf->read_addr;
		change++;
		dtv_pipe->ov_cnt = 0;
		dtv_pipe->dmae_cnt = 0;
	} else if (enable == 0 && dtv_pipe->ov_blt_addr) {
		dtv_pipe->ov_blt_addr = 0;
		dtv_pipe->dma_blt_addr = 0;
		change++;
	}
	pr_debug("%s: ov_blt_addr=%x\n", __func__, (int)dtv_pipe->ov_blt_addr);
	spin_unlock_irqrestore(&mdp_spin_lock, flag);

	if (!change)
		return;

	if (dtv_enabled)
		mdp4_overlay_dtv_wait4dmae(mfd);

	while (inpdw(MDP_BASE + 0x0018) & 0x12)
		;

	if (enable) {
		mdp4_overlayproc_cfg(dtv_pipe);
		mdp4_overlay_dmae_xy(dtv_pipe);
	} else {
		mdp4_overlay_dmae_xy(dtv_pipe);
		mdp4_overlayproc_cfg(dtv_pipe);
	}
}
Esempio n. 3
0
static void mdp4_dtv_do_blt(struct msm_fb_data_type *mfd, int enable)
{
	unsigned long flag;
	int change = 0;

	if (!mfd->ov1_wb_buf->phys_addr) {
		pr_debug("%s: no writeback buf assigned\n", __func__);
		return;
	}

#ifdef CONFIG_MACH_LGE
/* QCT Patch : Prevent kernel Crash (mdp4_overlay1_done_dtv()) */
	if (!dtv_pipe) {
		pr_debug("%s: no mixer1 base layer pipe allocated!\n",
			 __func__);
		return;
	}
#endif

	spin_lock_irqsave(&mdp_spin_lock, flag);
	if (enable && dtv_pipe->blt_addr == 0) {
		dtv_pipe->blt_addr = mfd->ov1_wb_buf->phys_addr;
		change++;
		dtv_pipe->ov_cnt = 0;
		dtv_pipe->dmae_cnt = 0;
	} else if (enable == 0 && dtv_pipe->blt_addr) {
		dtv_pipe->blt_addr = 0;
		change++;
	}
	pr_debug("%s: blt_addr=%x\n", __func__, (int)dtv_pipe->blt_addr);
	spin_unlock_irqrestore(&mdp_spin_lock, flag);

	if (!change)
		return;

	mdp4_overlay_dtv_wait4dmae(mfd);

	MDP_OUTP(MDP_BASE + DTV_BASE, 0);	/* stop dtv */
	msleep(20);
	mdp4_overlayproc_cfg(dtv_pipe);
	mdp4_overlay_dmae_xy(dtv_pipe);
	MDP_OUTP(MDP_BASE + DTV_BASE, 1);	/* start dtv */
}
Esempio n. 4
0
static void mdp4_overlay_dtv_wait4_ov_done(struct msm_fb_data_type *mfd,
        struct mdp4_overlay_pipe *pipe)
{
    u32 data = inpdw(MDP_BASE + DTV_BASE);

    if (mfd->ov_start)
        mfd->ov_start = false;
    else
        return;
    if (!(data & 0x1) || (pipe == NULL))
        return;
    if (!dtv_pipe) {
        pr_debug("%s: no mixer1 base layer pipe allocated!\n",
                 __func__);
        return;
    }

    wait_for_completion_timeout(&dtv_pipe->comp,
                                msecs_to_jiffies(VSYNC_PERIOD*2));
    mdp_disable_irq(MDP_OVERLAY1_TERM);

    if (dtv_pipe->blt_addr)
        mdp4_overlay_dtv_wait4dmae(mfd);
}