static void tegra132_memrange_init(struct memranges *map) { uint64_t start,end; const unsigned long devmem = MA_DEV | MA_S | MA_RW; const unsigned long cachedmem = MA_MEM | MA_NS | MA_RW; const unsigned long secure_mem = MA_MEM | MA_S | MA_RW; uintptr_t tz_base_mib; size_t tz_size_mib; memranges_init_empty(map); memory_in_range_below_4gb(&start,&end); /* Device memory below DRAM */ memranges_insert(map, 0, start * MiB, devmem); /* DRAM */ memranges_insert(map, start * MiB, (end-start) * MiB, cachedmem); memory_in_range_above_4gb(&start,&end); memranges_insert(map, start * MiB, (end-start) * MiB, cachedmem); /* SRAM */ memranges_insert(map, TEGRA_SRAM_BASE, TEGRA_SRAM_SIZE, cachedmem); /* Add TZ carveout. */ carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib); memranges_insert(map, tz_base_mib * MiB, tz_size_mib * MiB, secure_mem); }
void *cbmem_top(void) { static uintptr_t addr; if (addr == 0) { uintptr_t begin_mib; uintptr_t end_mib; memory_in_range_below_4gb(&begin_mib, &end_mib); /* Make sure we consume everything up to 4GiB. */ if (end_mib == 4096) addr = ~(uint32_t)0; else addr = end_mib << 20; } return (void *)addr; }
static void soc_read_resources(device_t dev) { unsigned long index = 0; int i; uintptr_t begin, end; size_t size; for (i = 0; i < CARVEOUT_NUM; i++) { carveout_range(i, &begin, &size); if (size == 0) continue; reserved_ram_resource(dev, index++, begin * KiB, size * KiB); } memory_in_range_below_4gb(&begin, &end); size = end - begin; ram_resource(dev, index++, begin * KiB, size * KiB); memory_in_range_above_4gb(&begin, &end); size = end - begin; ram_resource(dev, index++, begin * KiB, size * KiB); }