char* cpu_get_disassembly(memory_t *mem, uword_t addr) {
instruction_t instruction;
if (memory_read_byte(mem, addr) == CPU_EXTENDED_OPCODE)
instruction = cpu_get_extended_instruction(mem, addr);
else
instruction = cpu_get_instruction(mem, addr);
char *disassembly;
// Create the disassembly
switch (instruction.operand_length) {
case 0:
asprintf(&disassembly, instruction.disassembly, NULL);
break;
case 1:
asprintf(&disassembly, instruction.disassembly, memory_read_byte(mem, addr+1));
break;
case 2:
asprintf(&disassembly, instruction.disassembly, memory_read_word(mem, addr+1));
}
return disassembly;
}
static vmResult
emupio_filehandler(u32 code)
{
u16 rambase;
module_logger(&emuPIODSR, _L | L_3, _("handling code %d\n\n"), code);
/* get RAM base */
rambase = wp - 0xe0;
module_logger(&emuPIODSR, _L | L_2, "RAMbase=%04x\n", rambase);
if (code == D_PIO)
{
u16 pabaddr =
memory_read_word(rambase+0x56) -
memory_read_word(rambase+0x54) -
PABREC_SIZE;
u8 opcode;
u8 *fnptr;
fnptr = VDP_PTR(pabaddr+9);
opcode = *(fnptr-9);
/* illegal opcode? */
if (opcode > 9)
pab_set_vdp_error(fnptr, e_illegal);
else {
static void (*opcodehandlers[]) (u8 dev, u16 crubase, u8 *fn) = {
PIODSROpen, PIODSRClose, PIODSRRead, PIODSRWrite,
0 /*seek*/, 0 /*PIOLoad*/, 0 /*PIOSave*/, 0 /*delete*/,
0 /*scratch*/, 0 /*status*/
};
if (opcodehandlers[opcode] == 0) {
module_logger(&emuPIODSR, _L | L_2, _("unsupported operation %d on PIO/%d\n"), opcode, code);
pab_set_vdp_error(fnptr, e_illegal);
}
else {
module_logger(&emuPIODSR, _L | L_2, _("doing operation %d on PIO/%d\n"), opcode, code);
opcodehandlers[opcode] (code, memory_read_word(rambase + 0xF8), fnptr);
}
}
/* return, indicating that the DSR handled the operation */
register(11) += 2;
}
static WRITE16_HANDLER( protection_w )
{
asterix_state *state = (asterix_state *)space->machine->driver_data;
COMBINE_DATA(state->prot + offset);
if (offset == 1)
{
UINT32 cmd = (state->prot[0] << 16) | state->prot[1];
switch (cmd >> 24)
{
case 0x64:
{
UINT32 param1 = (memory_read_word(space, cmd & 0xffffff) << 16) | memory_read_word(space, (cmd & 0xffffff) + 2);
UINT32 param2 = (memory_read_word(space, (cmd & 0xffffff) + 4) << 16) | memory_read_word(space, (cmd & 0xffffff) + 6);
switch (param1 >> 24)
{
case 0x22:
{
int size = param2 >> 24;
param1 &= 0xffffff;
param2 &= 0xffffff;
while(size >= 0)
{
memory_write_word(space, param2, memory_read_word(space, param1));
param1 += 2;
param2 += 2;
size--;
}
break;
}
}
break;
}
}
}
static void memory_mapper_w(const address_space *space, struct memory_mapper_chip *chip, offs_t offset, UINT8 data)
{
UINT8 oldval;
/* wraps every 32 bytes */
offset &= 0x1f;
/* remember the previous value and swap in the new one */
oldval = chip->regs[offset];
chip->regs[offset] = data;
/* switch off the offset */
switch (offset)
{
case 0x02:
/* misc commands */
/* 00 - resume execution after 03 */
/* 03 - maybe controls halt and reset lines together? */
if ((oldval ^ chip->regs[offset]) & 3)
{
if ((chip->regs[offset] & 3) == 3)
fd1094_machine_init(chip->cpu);
/* fd1094_machine_init calls device_reset on the CPU, so we must do this afterwards */
cpu_set_input_line(chip->cpu, INPUT_LINE_RESET, (chip->regs[offset] & 3) == 3 ? ASSERT_LINE : CLEAR_LINE);
}
break;
case 0x03:
if (chip->sound_w)
(*chip->sound_w)(space->machine, data);
break;
case 0x04:
/* controls IRQ lines to 68000, negative logic -- write $B to signal IRQ4 */
if ((chip->regs[offset] & 7) != 7)
{
int irqnum;
for (irqnum = 0; irqnum < 8; irqnum++)
cpu_set_input_line(chip->cpu, irqnum, (irqnum == (~chip->regs[offset] & 7)) ? HOLD_LINE : CLEAR_LINE);
}
break;
case 0x05:
/* read/write control */
/* 01 - write data latched in 00,01 to 2 * (address in 0A,0B,0C) */
/* 02 - read data into latches 00,01 from 2 * (address in 07,08,09) */
if (data == 0x01)
{
const address_space *targetspace = cpu_get_address_space(chip->cpu, ADDRESS_SPACE_PROGRAM);
offs_t addr = (chip->regs[0x0a] << 17) | (chip->regs[0x0b] << 9) | (chip->regs[0x0c] << 1);
memory_write_word(targetspace, addr, (chip->regs[0x00] << 8) | chip->regs[0x01]);
}
else if (data == 0x02)
{
const address_space *targetspace = cpu_get_address_space(chip->cpu, ADDRESS_SPACE_PROGRAM);
offs_t addr = (chip->regs[0x07] << 17) | (chip->regs[0x08] << 9) | (chip->regs[0x09] << 1);
UINT16 result;
result = memory_read_word(targetspace, addr);
chip->regs[0x00] = result >> 8;
chip->regs[0x01] = result;
}
break;
case 0x07: case 0x08: case 0x09:
/* writes here latch a 68000 address for writing */
break;
case 0x0a: case 0x0b: case 0x0c:
/* writes here latch a 68000 address for reading */
break;
case 0x10: case 0x11:
case 0x12: case 0x13:
case 0x14: case 0x15:
case 0x16: case 0x17:
case 0x18: case 0x19:
case 0x1a: case 0x1b:
case 0x1c: case 0x1d:
case 0x1e: case 0x1f:
if (oldval != data)
update_memory_mapping(space->machine, chip, 1);
break;
default:
logerror("Unknown memory_mapper_w to address %02X = %02X\n", offset, data);
break;
}
}
void ld_hl_nn(memory_t *mem, registers_t *regs) {
// Get operands, here 8 bytes.
regs->HL = memory_read_word(mem, (regs->PC)+1);
regs->PC += 3;
}
