/* #ifdef CONFIG_SPD_EEPROM
ret = spd_sdram ();
#else
ret = init_sdram_static_settings();
#endif
*/
ret = init_sdram_static_settings();
return ret;
}
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CFG_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
}
#endif
#if 0 /* test-only !!! */
int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong ap, cr;
printf("\nEBC registers for PPC405GP:\n");
mfebc(pb0ap, ap); mfebc(pb0cr, cr);
printf("0: AP=%08lx CP=%08lx\n", ap, cr);
mfebc(pb1ap, ap); mfebc(pb1cr, cr);
printf("1: AP=%08lx CP=%08lx\n", ap, cr);
mfebc(pb2ap, ap); mfebc(pb2cr, cr);
printf("2: AP=%08lx CP=%08lx\n", ap, cr);
mfebc(pb3ap, ap); mfebc(pb3cr, cr);
printf("3: AP=%08lx CP=%08lx\n", ap, cr);
mfebc(pb4ap, ap); mfebc(pb4cr, cr);
printf("4: AP=%08lx CP=%08lx\n", ap, cr);
printf("\n");
return 0;
}
/* #ifdef CONFIG_SPD_EEPROM
ret = spd_sdram ();
#else
ret = init_sdram_static_settings();
#endif
*/
ret = init_sdram_static_settings();
return ret;
}
#if 0 /* test-only !!! */
int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong ap, cr;
printf("\nEBC registers for PPC405GP:\n");
mfebc(PB0AP, ap); mfebc(PB0CR, cr);
printf("0: AP=%08lx CP=%08lx\n", ap, cr);
mfebc(PB1AP, ap); mfebc(PB1CR, cr);
printf("1: AP=%08lx CP=%08lx\n", ap, cr);
mfebc(PB2AP, ap); mfebc(PB2CR, cr);
printf("2: AP=%08lx CP=%08lx\n", ap, cr);
mfebc(PB3AP, ap); mfebc(PB3CR, cr);
printf("3: AP=%08lx CP=%08lx\n", ap, cr);
mfebc(PB4AP, ap); mfebc(PB4CR, cr);
printf("4: AP=%08lx CP=%08lx\n", ap, cr);
printf("\n");
return 0;
}
int misc_init_r(void)
{
u32 pbcr;
int size_val = 0;
u32 reg;
unsigned long usb2d0cr = 0;
unsigned long usb2phy0cr, usb2h0cr = 0;
unsigned long sdr0_pfc1, sdr0_srst;
/*
* FLASH stuff...
*/
/* Re-do sizing to get full correct info */
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
mfebc(PB0CR, pbcr);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtebc(PB0CR, pbcr);
/*
* Re-check to get correct base address
*/
flash_get_size(gd->bd->bi_flashstart, 0);
/* Monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
&flash_info[cfi_flash_num_flash_banks - 1]);
/* Env protection ON by default */
flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
&flash_info[cfi_flash_num_flash_banks - 1]);
/*
* USB suff...
*/
/* Reset USB */
/* Reset of USB2PHY0 must be active at least 10 us */
mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
udelay(2000);
mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
udelay(2000);
/* Errata CHIP_6 */
/* 1. Set internal PHY configuration */
/* SDR Setting */
mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_USB0, usb2d0cr);
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr);
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
/*
* An 8-bit/60MHz interface is the only possible alternative
* when connecting the Device to the PHY
*/
usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
mtsdr(SDR0_PFC1, sdr0_pfc1);
mtsdr(SDR0_USB0, usb2d0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2H0CR, usb2h0cr);
/* 2. De-assert internal PHY reset */
mfsdr(SDR0_SRST1, sdr0_srst);
sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
mtsdr(SDR0_SRST1, sdr0_srst);
/* 3. Wait for more than 1 ms */
udelay(2000);
/* 4. De-assert USB 2.0 Host main reset */
mfsdr(SDR0_SRST0, sdr0_srst);
sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
mtsdr(SDR0_SRST0, sdr0_srst);
udelay(1000);
/* 5. De-assert reset of OPB2 cores */
mfsdr(SDR0_SRST1, sdr0_srst);
sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
mtsdr(SDR0_SRST1, sdr0_srst);
udelay(1000);
/* 6. Set EHCI Configure FLAG */
/* 7. Reassert internal PHY reset: */
mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
udelay(1000);
/*
* Clear resets
*/
mtsdr(SDR0_SRST1, 0x00000000);
mtsdr(SDR0_SRST0, 0x00000000);
printf("USB: Host(int phy) Device(ext phy)\n");
/*
* Clear PLB4A0_ACR[WRP]
* This fix will make the MAL burst disabling patch for the Linux
* EMAC driver obsolete.
*/
reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
mtdcr(PLB4A0_ACR, reg);
/*
* Init matrix keyboard
*/
misc_init_r_kbd();
return 0;
}
/*---------------------------------------------------------------------------+
| misc_init_r.
+---------------------------------------------------------------------------*/
int misc_init_r(void)
{
u32 pbcr;
int size_val = 0;
u32 reg;
unsigned long usb2d0cr = 0;
unsigned long usb2phy0cr, usb2h0cr = 0;
unsigned long sdr0_pfc1;
/*
* FLASH stuff...
*/
/* Re-do sizing to get full correct info */
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
mfebc(pb0cr, pbcr);
switch (gd->bd->bi_flashsize) {
case 1 << 20:
size_val = 0;
break;
case 2 << 20:
size_val = 1;
break;
case 4 << 20:
size_val = 2;
break;
case 8 << 20:
size_val = 3;
break;
case 16 << 20:
size_val = 4;
break;
case 32 << 20:
size_val = 5;
break;
case 64 << 20:
size_val = 6;
break;
case 128 << 20:
size_val = 7;
break;
}
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtebc(pb0cr, pbcr);
/*
* Re-check to get correct base address
*/
flash_get_size(gd->bd->bi_flashstart, 0);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-CFG_MONITOR_LEN,
0xffffffff,
&flash_info[1]);
/* Env protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR_REDUND,
CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
&flash_info[1]);
/*
* USB suff...
*/
/* SDR Setting */
mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_USB0, usb2d0cr);
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
/* An 8-bit/60MHz interface is the only possible alternative
when connecting the Device to the PHY */
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
mtsdr(SDR0_PFC1, sdr0_pfc1);
mtsdr(SDR0_USB0, usb2d0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2H0CR, usb2h0cr);
/*
* Clear resets
*/
udelay (1000);
mtsdr(SDR0_SRST1, 0x00000000);
udelay (1000);
mtsdr(SDR0_SRST0, 0x00000000);
printf("USB: Host(int phy) Device(ext phy)\n");
/*
* Clear PLB4A0_ACR[WRP]
* This fix will make the MAL burst disabling patch for the Linux
* EMAC driver obsolete.
*/
reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
mtdcr(plb4_acr, reg);
/*
* Init matrix keyboard
*/
misc_init_r_kbd();
return 0;
}
int misc_init_r(void)
{
u32 pbcr;
int size_val = 0;
u32 post_magic;
u32 post_val;
post_magic = in_be32((void *)CONFIG_SYS_POST_MAGIC);
post_val = in_be32((void *)CONFIG_SYS_POST_VAL);
if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) {
/*
* Set special bootline bootparameter to pass this POST boot
* mode to Linux to reset the username/password
*/
setenv("addmisc", "setenv bootargs \\${bootargs} factory_reset=yes");
/*
* Normally don't run POST tests, only when enabled
* via the sw-reset button. So disable further tests
* upon next bootup here.
*/
out_be32((void *)CONFIG_SYS_POST_VAL, REBOOT_NOP);
} else {
/*
* Only run POST when initiated via the sw-reset button mechanism
*/
post_word_store(0);
}
/*
* Get current time
*/
start_time = get_timer(0);
/*
* FLASH stuff...
*/
/* Re-do sizing to get full correct info */
/* adjust flash start and offset */
mfebc(PB0CR, pbcr);
switch (gd->bd->bi_flashsize) {
case 1 << 20:
size_val = 0;
break;
case 2 << 20:
size_val = 1;
break;
case 4 << 20:
size_val = 2;
break;
case 8 << 20:
size_val = 3;
break;
case 16 << 20:
size_val = 4;
break;
case 32 << 20:
size_val = 5;
break;
case 64 << 20:
size_val = 6;
break;
case 128 << 20:
size_val = 7;
break;
}
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtebc(PB0CR, pbcr);
/*
* Re-check to get correct base address
*/
flash_get_size(gd->bd->bi_flashstart, 0);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
/* Env protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR_REDUND,
CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
return 0;
}
