static int __init pxa930_init(void) { if (cpu_is_pxa930() || cpu_is_pxa935() || cpu_is_pxa950()) { mfp_init_base(io_p2v(MFPR_BASE)); mfp_init_addr(pxa930_mfp_addr_map); } if (cpu_is_pxa935()) mfp_init_addr(pxa935_mfp_addr_map); return 0; }
static int __init pxa300_init(void) { if (cpu_is_pxa300() || cpu_is_pxa310()) { mfp_init_base(io_p2v(MFPR_BASE)); mfp_init_addr(pxa300_mfp_addr_map); clks_register(ARRAY_AND_SIZE(common_clkregs)); } if (cpu_is_pxa310()) { mfp_init_addr(pxa310_mfp_addr_map); clks_register(ARRAY_AND_SIZE(pxa310_clkregs)); } return 0; }
static int __init pxa95x_init(void) { int ret = 0, i; if (cpu_is_pxa95x()) { mfp_init_base(io_p2v(MFPR_BASE)); mfp_init_addr(pxa95x_mfp_addr_map); reset_status = ARSR; /* */ ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); clkdev_add_table(pxa95x_clkregs, ARRAY_SIZE(pxa95x_clkregs)); if ((ret = pxa_init_dma(IRQ_DMA, 32))) return ret; register_syscore_ops(&pxa_irq_syscore_ops); register_syscore_ops(&pxa3xx_clock_syscore_ops); ret = platform_add_devices(devices, ARRAY_SIZE(devices)); } return ret; }
static int __init pxa95x_init(void) { int ret = 0, i; if (cpu_is_pxa95x()) { mfp_init_base(io_p2v(MFPR_BASE)); mfp_init_addr(pxa95x_mfp_addr_map); reset_status = ARSR; /* * clear RDH bit every time after reset * * Note: the last 3 bits DxS are write-1-to-clear so carefully * preserve them here in case they will be referenced later */ ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); clkdev_add_table(pxa95x_clkregs, ARRAY_SIZE(pxa95x_clkregs)); if ((ret = pxa_init_dma(IRQ_DMA, 32))) return ret; register_syscore_ops(&pxa_irq_syscore_ops); register_syscore_ops(&pxa_gpio_syscore_ops); register_syscore_ops(&pxa3xx_clock_syscore_ops); ret = platform_add_devices(devices, ARRAY_SIZE(devices)); } return ret; }
static int __init pxa930_init(void) { int ret = 0; if (cpu_is_pxa93x()) { mfp_init_base(io_p2v(MFPR_BASE)); mfp_init_addr(pxa930_mfp_addr_map); platform_device_add_data(&pxa93x_device_gpio, &pxa93x_gpio_pdata, sizeof(pxa93x_gpio_pdata)); ret = platform_device_register(&pxa93x_device_gpio); } if (cpu_is_pxa935()) mfp_init_addr(pxa935_mfp_addr_map); return 0; }
static int __init pxa320_init(void) { if (cpu_is_pxa320()) { mfp_init_base(io_p2v(MFPR_BASE)); mfp_init_addr(pxa320_mfp_addr_map); clkdev_add_table(ARRAY_AND_SIZE(pxa320_clkregs)); } return 0; }
static int __init pxa168_init(void) { if (cpu_is_pxa168()) { mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(pxa168_mfp_addr_map); pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); clks_register(ARRAY_AND_SIZE(pxa168_clkregs)); } return 0; }
static int __init pxa168_init(void) { if (cpu_is_pxa168()) { mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(pxa168_mfp_addr_map); pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); pxa168_clk_init(); } return 0; }
static int __init pxa910_init(void) { if (cpu_is_pxa910()) { mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(pxa910_mfp_addr_map); pxa_init_dma(IRQ_PXA910_DMA_INT0, 32); clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs)); } return 0; }
static int __init mmp2_init(void) { if (cpu_is_mmp2()) { #ifdef CONFIG_CACHE_TAUROS2 tauros2_init(); #endif mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(mmp2_addr_map); pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16); clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs)); } return 0; }
static int __init pxa910_init(void) { if (cpu_is_pxa910()) { #ifdef CONFIG_CACHE_TAUROS2 tauros2_init(0); #endif mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(pxa910_mfp_addr_map); pxa_init_dma(IRQ_PXA910_DMA_INT0, 32); pxa910_clk_init(); } return 0; }
static int __init pxa910_init(void) { if (cpu_is_pxa910()) { #ifdef CONFIG_CACHE_TAUROS2 tauros2_init(0); #endif mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(pxa910_mfp_addr_map); pxa910_clk_init(APB_PHYS_BASE + 0x50000, AXI_PHYS_BASE + 0x82800, APB_PHYS_BASE + 0x15000, APB_PHYS_BASE + 0x3b000); } return 0; }