/**
* md_mic_dma_chan_init_attr - Set channel attributes like owner and endianness
* @chan: The DMA channel handle
*/
void md_mic_dma_chan_init_attr(struct mic_dma_device *dma_dev,
struct md_mic_dma_chan *chan)
{
uint32_t dcr;
CHECK_CHAN(chan);
dcr = mic_sbox_read_mmio(dma_dev->mm_sbox, SBOX_DCR);
dcr = chan_to_dcr_mask(dcr, chan, dma_dev);
mic_sbox_write_mmio(dma_dev->mm_sbox, SBOX_DCR, dcr);
}
/*
* dma_resume: DMA tasks after wake up from low power state.
* @dma_handle: Handle for a DMA driver context.
*
* Performs the following tasks before the device transitions
* from a low power state to active state:
* 1) As a test, reset the value in DMA configuration register.
* 2) Reset the next_write_index for the DMA descriptor ring to 0
* since the DMA channel will be reset shortly.
* 3) Reinitialize the DMA MD layer for the channel.
*
* Return: none
* Notes:
* Notes: Invoked only on MIC.
*/
void dma_resume(mic_dma_handle_t dma_handle)
{
int i;
struct dma_channel *ch;
struct mic_dma_ctx_t *dma_ctx = (struct mic_dma_ctx_t *)dma_handle;
struct mic_dma_device *dma_dev = &dma_ctx->dma_dev;
/* TODO: Remove test write to SBOX_DCR */
mic_sbox_write_mmio(dma_dev->mm_sbox, SBOX_DCR, 0);
for (i = 0; i < MAX_NUM_DMA_CHAN; i++) {
ch = &dma_ctx->dma_channels[i];
ch->next_write_index = 0;
md_mic_dma_chan_init_attr(dma_dev, ch->chan);
md_mic_dma_chan_setup(dma_ctx, ch);
}
}
/**
* md_mic_dma_enable_chan - Enable/disable the DMA channel
* @chan_num: The DMA channel
* @enable: enable/disable
*
* Must set desc ring and update head pointer only
* after disabling the channel
*/
void md_mic_dma_enable_chan(struct mic_dma_device *dma_dev,
uint32_t chan_num, bool enable)
{
uint32_t dcr = mic_sbox_read_mmio(dma_dev->mm_sbox, SBOX_DCR);
/*
* There is a separate bit for every channel.
* Look up sboxDcrReg.
*/
if (enable) {
dcr |= 2 << (chan_num << 1);
} else {
dcr &= ~(2 << (chan_num << 1));
}
mic_sbox_write_mmio(dma_dev->mm_sbox, SBOX_DCR, dcr);
}
