static int midas_wm1811_aif1_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
struct snd_soc_dai *codec_dai = rtd->codec_dai;
unsigned int pll_out;
int ret;
dev_info(codec_dai->dev, "%s ++\n", __func__);
/* AIF1CLK should be >=3MHz for optimal performance */
if (params_rate(params) == 8000 || params_rate(params) == 11025)
pll_out = params_rate(params) * 512;
else
pll_out = params_rate(params) * 256;
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM);
if (ret < 0)
return ret;
/* Set the cpu DAI configuration */
ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM);
if (ret < 0)
return ret;
#ifndef SND_USE_BIAS_LEVEL
/* Switch the FLL */
ret = snd_soc_dai_set_pll(codec_dai, WM8994_FLL1,
WM8994_FLL_SRC_MCLK1, MIDAS_DEFAULT_MCLK1,
pll_out);
if (ret < 0)
dev_err(codec_dai->dev, "Unable to start FLL1: %d\n", ret);
ret = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_FLL1,
pll_out, SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(codec_dai->dev, "Unable to switch to FLL1: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_OPCLK,
0, MOD_OPCLK_PCLK);
if (ret < 0)
return ret;
#else
midas_start_fll1(codec_dai);
#endif
if (ret < 0)
return ret;
dev_info(codec_dai->dev, "%s --\n", __func__);
return 0;
}
static int midas_wm1811_aif1_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
struct snd_soc_dai *codec_dai = rtd->codec_dai;
unsigned int pll_out;
int ret;
/* AIF1CLK should be >=3MHz for optimal performance */
if (params_rate(params) == 8000 || params_rate(params) == 11025)
pll_out = params_rate(params) * 512;
else
pll_out = params_rate(params) * 256;
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM);
if (ret < 0)
return ret;
/* Set the cpu DAI configuration */
ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM);
if (ret < 0)
return ret;
#if 0
ret = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_FLL1,
pll_out, SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
ret = snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_OPCLK,
0, MOD_OPCLK_PCLK);
if (ret < 0)
return ret;
#else
midas_start_fll1(codec_dai);
#endif
if (ret < 0)
return ret;
return 0;
}
static int midas_set_bias_level(struct snd_soc_card *card,
struct snd_soc_dapm_context *dapm,
enum snd_soc_bias_level level)
{
struct snd_soc_dai *aif1_dai = card->rtd[0].codec_dai;
if (dapm->dev != aif1_dai->dev)
return 0;
switch (level) {
case SND_SOC_BIAS_PREPARE:
midas_start_fll1(card->rtd[0].codec_dai);
break;
default:
break;
}
return 0;
}
static int midas_wm1811_aif2_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->codec_dai;
int ret;
int prate;
int bclk;
dev_info(codec_dai->dev, "%s ++\n", __func__);
prate = params_rate(params);
switch (params_rate(params)) {
case 8000:
case 16000:
break;
default:
dev_warn(codec_dai->dev, "Unsupported LRCLK %d, falling back to 8000Hz\n",
(int)params_rate(params));
prate = 8000;
}
#if defined(CONFIG_LTE_MODEM_CMC221) || defined(CONFIG_MACH_M0_CTC)
#if defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_BAFFIN_KOR_LGT)
/* Set the codec DAI configuration */
if (aif2_mode == 0) {
if (kpcs_mode == 1)
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBS_CFS);
else
ret = snd_soc_dai_set_fmt(codec_dai,
SND_SOC_DAIFMT_DSP_A
| SND_SOC_DAIFMT_IB_NF
| SND_SOC_DAIFMT_CBS_CFS);
} else
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM);
#else
if (aif2_mode == 0)
/* Set the codec DAI configuration */
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A
| SND_SOC_DAIFMT_IB_NF
| SND_SOC_DAIFMT_CBS_CFS);
else
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A
| SND_SOC_DAIFMT_IB_NF
| SND_SOC_DAIFMT_CBM_CFM);
#endif
#else
/* Set the codec DAI configuration, aif2_mode:0 is slave */
if (aif2_mode == 0)
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBS_CFS);
else
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM);
#endif
if (ret < 0)
return ret;
#if defined(CONFIG_LTE_MODEM_CMC221)
if (kpcs_mode == 1) {
switch (prate) {
case 8000:
bclk = 256000;
break;
case 16000:
bclk = 512000;
break;
default:
return -EINVAL;
}
} else {
bclk = 2048000;
}
#elif defined(CONFIG_MACH_M0_CTC)
bclk = 2048000;
#else
switch (prate) {
case 8000:
bclk = 256000;
break;
case 16000:
bclk = 512000;
break;
default:
return -EINVAL;
}
#endif
#ifdef SND_USE_BIAS_LEVEL
if (!midas_fll1_active)
midas_start_fll1(midas_aif1_dai);
#endif
if (aif2_mode == 0) {
ret = snd_soc_dai_set_pll(codec_dai, WM8994_FLL2,
WM8994_FLL_SRC_BCLK,
bclk, prate * 256);
} else {
ret = snd_soc_dai_set_pll(codec_dai, WM8994_FLL2,
WM8994_FLL_SRC_MCLK1,
MIDAS_DEFAULT_MCLK1, prate * 256);
}
if (ret < 0)
dev_err(codec_dai->dev, "Unable to configure FLL2: %d\n", ret);
ret = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_FLL2,
prate * 256, SND_SOC_CLOCK_IN);
if (ret < 0)
dev_err(codec_dai->dev, "Unable to switch to FLL2: %d\n", ret);
dev_info(codec_dai->dev, "%s --\n", __func__);
return 0;
}
