void mips_intr_init() {
/*
* Enable Vectored Interrupt Mode as described in „MIPS32® 24KETM Processor
* Core Family Software User’s Manual”, chapter 6.3.1.2.
*/
/* The location of exception vectors is set to EBase. */
mips32_set_c0(C0_EBASE, _ebase);
mips32_bc_c0(C0_STATUS, SR_BEV);
/* Use the special interrupt vector at EBase + 0x200. */
mips32_bs_c0(C0_CAUSE, CR_IV);
/* Set vector spacing to 0. */
mips32_set_c0(C0_INTCTL, INTCTL_VS_0);
}
void tlb_init() {
tlb_invalidate_all();
/* Shift C0_CONTEXT left, because we shift it right in tlb_refill_handler.
* This is little hack to make page table sized 4MB, but causes us to
* keep PTE in KSEG2. */
mips32_set_c0(C0_CONTEXT, PTE_BASE << 1);
}
void mips_irq_handler(exc_frame_t *frame) {
unsigned pending = (frame->cause & frame->sr) & CR_IP_MASK;
for (int i = 7; i >= 0; i--) {
unsigned irq = CR_IP0 << i;
if (pending & irq) {
irq_handler_t handler = irq_handlers[i];
if (handler != NULL) {
handler();
} else {
log("Spurious hardware interrupt #%d!", i);
}
pending &= ~irq;
}
}
mips32_set_c0(C0_CAUSE, frame->cause & ~CR_IP_MASK);
}
static void set_asid(uint8_t asid) {
mips32_set_c0(C0_ENTRYHI, asid);
}
void set_active_pmap(pmap_t *pmap) {
active_pmap = pmap;
mips32_set_c0(C0_ENTRYHI, pmap->asid);
}
