void extcl_cpu_wr_mem_233(WORD address, BYTE value) { BYTE save = value; value &= 0x1F; if (save & 0x20) { control_bank(info.prg.rom.max.banks_16k) map_prg_rom_8k(2, 0, value); map_prg_rom_8k(2, 2, value); } else { value >>= 1; control_bank(info.prg.rom.max.banks_32k) map_prg_rom_8k(4, 0, value); } map_prg_rom_8k_update(); switch ((save & 0xC0) >> 6) { case 0: mirroring_SCR0x3_SCR1x1(); break; case 1: mirroring_V(); break; case 2: mirroring_H(); break; case 3: mirroring_SCR1(); break; } }
void extcl_cpu_wr_mem_74x161x161x32(WORD address, BYTE value) { /* bus conflict */ const BYTE save = value &= prg_rom_rd(address); DBWORD bank; if (type == IC74X161X161X32B) { if (value & 0x80) { mirroring_SCR1(); } else { mirroring_SCR0(); } } control_bank_with_AND(0x0F, info.chr.rom[0].max.banks_8k) bank = value << 13; chr.bank_1k[0] = chr_chip_byte_pnt(0, bank); chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400); chr.bank_1k[2] = chr_chip_byte_pnt(0, bank | 0x0800); chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0C00); chr.bank_1k[4] = chr_chip_byte_pnt(0, bank | 0x1000); chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x1400); chr.bank_1k[6] = chr_chip_byte_pnt(0, bank | 0x1800); chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x1C00); value = save >> 4; control_bank(info.prg.rom[0].max.banks_16k) map_prg_rom_8k(2, 0, value); map_prg_rom_8k_update(); }
void extcl_cpu_wr_mem_AxROM(WORD address, BYTE value) { /* bus conflict */ if (info.mapper.submapper == AMROM) { value &= prg_rom_rd(address); } if (value & 0x10) { mirroring_SCR0(); } else { mirroring_SCR1(); } control_bank_with_AND(0x0F, info.prg.rom.max.banks_32k) map_prg_rom_8k(4, 0, value); map_prg_rom_8k_update(); }
static void INLINE sync_83(void) { WORD value; switch (m83.mode & 0x03) { case 0: mirroring_V(); break; case 1: mirroring_H(); break; case 2: mirroring_SCR0(); break; case 3: mirroring_SCR1(); break; } if (m83.is2kbank && !m83.isnot2kbank) { SDBWORD bank; value = m83.reg[0]; control_bank(info.chr.rom.max.banks_2k) bank = value << 11; chr.bank_1k[0] = chr_chip_byte_pnt(0, bank); chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400); value = m83.reg[1]; control_bank(info.chr.rom.max.banks_2k) bank = value << 11; chr.bank_1k[2] = chr_chip_byte_pnt(0, bank); chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0400); value = m83.reg[6]; control_bank(info.chr.rom.max.banks_2k) bank = value << 11; chr.bank_1k[4] = chr_chip_byte_pnt(0, bank); chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x0400); value = m83.reg[7]; control_bank(info.chr.rom.max.banks_2k) bank = value << 11; chr.bank_1k[6] = chr_chip_byte_pnt(0, bank); chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x0400); } else { BYTE i; for (i = 0; i < 8; i++) { value = ((m83.bank << 4) & 0x0300) | m83.reg[i]; control_bank(info.chr.rom.max.banks_1k) chr.bank_1k[i] = chr_chip_byte_pnt(0, value << 10); } } if (m83.mode & 0x40) { value = (m83.bank & 0x3F); control_bank(info.prg.rom.max.banks_16k) map_prg_rom_8k(2, 0, value); value = (m83.bank & 0x30) | 0x0F; control_bank(info.prg.rom.max.banks_16k) map_prg_rom_8k(2, 2, value); } else { value = m83.reg[8]; control_bank(info.prg.rom.max.banks_8k) map_prg_rom_8k(1, 0, value); value = m83.reg[9]; control_bank(info.prg.rom.max.banks_8k) map_prg_rom_8k(1, 1, value); value = m83.reg[10]; control_bank(info.prg.rom.max.banks_8k) map_prg_rom_8k(1, 2, value); map_prg_rom_8k(1, 3, info.prg.rom.max.banks_8k); } map_prg_rom_8k_update(); }