void mite_release_channel(struct mite_channel *mite_chan)
{
struct mite_struct *mite = mite_chan->mite;
unsigned long flags;
/* spin lock to prevent races with mite_request_channel */
spin_lock_irqsave(&mite->lock, flags);
if (mite->channel_allocated[mite_chan->channel]) {
mite_dma_disarm(mite_chan);
mite_dma_reset(mite_chan);
/*
* disable all channel's interrupts (do it after disarm/reset so
* MITE_CHCR reg isn't changed while dma is still active!)
*/
writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
mite->channel_allocated[mite_chan->channel] = 0;
mite_chan->ring = NULL;
mmiowb();
}
spin_unlock_irqrestore(&mite->lock, flags);
}
int ni_tio_cancel(struct ni_gpct *counter)
{
unsigned int cidx = counter->counter_index;
unsigned long flags;
ni_tio_arm(counter, false, 0);
spin_lock_irqsave(&counter->lock, flags);
if (counter->mite_chan)
mite_dma_disarm(counter->mite_chan);
spin_unlock_irqrestore(&counter->lock, flags);
ni_tio_configure_dma(counter, false, false);
ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx),
GI_GATE_INTERRUPT_ENABLE(cidx), 0x0);
return 0;
}
int ni_tio_cancel(struct ni_gpct *counter)
{
unsigned cidx = counter->counter_index;
unsigned long flags;
ni_tio_arm(counter, 0, 0);
spin_lock_irqsave(&counter->lock, flags);
if (counter->mite_chan)
mite_dma_disarm(counter->mite_chan);
spin_unlock_irqrestore(&counter->lock, flags);
ni_tio_configure_dma(counter, 0, 0);
ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx),
Gi_Gate_Interrupt_Enable_Bit(cidx), 0x0);
return 0;
}
int ni_tio_cancel(struct ni_gpct *counter)
{
unsigned long flags;
ni_tio_arm(counter, 0, 0);
comedi_spin_lock_irqsave(&counter->lock, flags);
if (counter->mite_chan) {
mite_dma_disarm(counter->mite_chan);
}
comedi_spin_unlock_irqrestore(&counter->lock, flags);
ni_tio_configure_dma(counter, 0, 0);
ni_tio_set_bits(counter,
NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index),
Gi_Gate_Interrupt_Enable_Bit(counter->counter_index), 0x0);
return 0;
}
static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev)
{
unsigned long flags;
spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
if (devpriv->di_mite_chan) {
mite_dma_disarm(devpriv->di_mite_chan);
mite_dma_reset(devpriv->di_mite_chan);
mite_release_channel(devpriv->di_mite_chan);
devpriv->di_mite_chan = NULL;
writeb(primary_DMAChannel_bits(0) |
secondary_DMAChannel_bits(0),
devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
mmiowb();
}
spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
}
void mite_release_channel(struct mite_channel *mite_chan)
{
struct mite_struct *mite = mite_chan->mite;
unsigned long flags;
spin_lock_irqsave(&mite->lock, flags);
if (mite->channel_allocated[mite_chan->channel]) {
mite_dma_disarm(mite_chan);
mite_dma_reset(mite_chan);
writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
mite->channel_allocated[mite_chan->channel] = 0;
mite_chan->ring = NULL;
mmiowb();
}
spin_unlock_irqrestore(&mite->lock, flags);
}
