/*
* Move args to registers and emit expressions bottom-up.
*/
static void
fixargs(NODE *p)
{
NODE *r;
if (p->n_op == CM) {
fixargs(p->n_left);
r = p->n_right;
if (r->n_op == STARG)
regnum = 9; /* end of register list */
else if (regnum + szty(r->n_type) > 8)
p->n_right = block(FUNARG, r, NIL, r->n_type,
r->n_df, r->n_sue);
else
p->n_right = buildtree(ASSIGN, mkreg(r, regnum), r);
} else {
if (p->n_op == STARG) {
regnum = 9; /* end of register list */
} else {
r = talloc();
*r = *p;
r = buildtree(ASSIGN, mkreg(r, regnum), r);
*p = *r;
nfree(r);
}
r = p;
}
regnum += szty(r->n_type);
}
static void progbeg(int argc, char *argv[])
{
int i;
{
union
{
char c;
int i;
} u;
u.i = 0;
u.c = 1;
swap = ((int) (u.i == 1)) != IR->little_endian;
}
parseflags(argc, argv);
//put both ints and floats into IREG set
reg[RGA] = mkreg("A", RGA, 1, IREG);
reg[RGB] = mkreg("B", RGB, 1, IREG);
reg[RGC] = mkreg("C", RGC, 1, IREG);
reg[RGX] = mkreg("X", RGX, 1, IREG);
reg[RGY] = mkreg("Y", RGY, 1, IREG);
reg[RGZ] = mkreg("Z", RGZ, 1, IREG);
reg[RGI] = mkreg("I", RGI, 1, IREG);
regw = mkwildcard(reg);
tmask[IREG] = TMP_REG;
vmask[IREG] = VAR_REG;
tmask[FREG] = 0;
vmask[FREG] = 0;
print(";\n;DCPU-16 ASM Generated by LCC 4.2 (dcpu16-lcc v0.2)\n;\n");
print("JSR _global_main\n");
}
