/* Called from board_mmc_init during startup. Can be called multiple times
* depending on the number of slots available on board and controller
*/
int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host)
{
struct mmc *mmc;
mmc = malloc(sizeof(struct mmc));
memset(mmc, 0, sizeof(struct mmc));
sprintf(mmc->name, "davinci");
mmc->priv = host;
mmc->send_cmd = dmmc_send_cmd;
mmc->set_ios = dmmc_set_ios;
mmc->init = dmmc_init;
mmc->f_min = 200000;
mmc->f_max = 52000000;
mmc->voltages = host->voltages;
mmc->host_caps = host->host_caps | MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
#ifdef CONFIG_MMC_MBLOCK
mmc->b_max = DAVINCI_MAX_BLOCKS;
#endif
mmc_register(mmc);
return 0;
}
int omap_mmc_init(int dev_index)
{
struct mmc *mmc;
mmc = &hsmmc_dev[dev_index];
sprintf(mmc->name, "OMAP SD/MMC");
mmc->send_cmd = mmc_send_cmd;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_init_setup;
switch (dev_index) {
case 0:
mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE;
break;
case 1:
mmc->priv = (hsmmc_t *)OMAP_HSMMC2_BASE;
break;
case 2:
mmc->priv = (hsmmc_t *)OMAP_HSMMC3_BASE;
break;
default:
mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE;
return 1;
}
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
mmc->f_min = 400000;
mmc->f_max = 52000000;
mmc_register(mmc);
return 0;
}
static void board_mmc_register(unsigned port)
{
AML_CARD_SD_INFO_t *aml_priv=cpu_sdio_get(port);
if(aml_priv==NULL)
return;
struct mmc *mmc = (struct mmc *)malloc(sizeof(struct mmc));
strncpy(mmc->name,aml_priv->name,31);
mmc->priv = aml_priv;
aml_priv->removed_flag = 1;
aml_priv->inited_flag = 0;
aml_priv->sdio_init=sdio_init;
aml_priv->sdio_detect=sdio_detect;
aml_priv->sdio_pwr_off=sdio_pwr_off;
aml_priv->sdio_pwr_on=sdio_pwr_on;
aml_priv->sdio_pwr_prepare=sdio_pwr_prepare;
mmc->send_cmd = aml_sd_send_cmd;
mmc->set_ios = aml_sd_cfg_swth;
mmc->init = aml_sd_init;
mmc->rca = 1;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS;
//mmc->host_caps = MMC_MODE_4BIT;
mmc->bus_width = 1;
mmc->clock = 200000;
mmc->f_min = 200000;
mmc->f_max = 24000000;
mmc_register(mmc);
}
/*
* This is the only exported function
*
* Call it with the MCI register base address
*/
int atmel_mci_init(void *regs)
{
struct mmc *mmc = malloc(sizeof(struct mmc));
if (!mmc)
return -1;
strcpy(mmc->name, "mci");
mmc->priv = regs;
mmc->send_cmd = mci_send_cmd;
mmc->set_ios = mci_set_ios;
mmc->init = mci_init;
mmc->getcd = NULL;
mmc->getwp = NULL;
/* need to be able to pass these in on a board by board basis */
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->host_caps = MMC_MODE_4BIT;
/*
* min and max frequencies determined by
* max and min of clock divider
*/
mmc->f_min = get_mci_clk_rate() / (2*256);
mmc->f_max = get_mci_clk_rate() / (2*1);
mmc->b_max = 0;
mmc_register(mmc);
return 0;
}
int mmcif_mmc_init(void)
{
int ret = 0;
struct mmc *mmc;
struct sh_mmcif_host *host = NULL;
mmc = malloc(sizeof(struct mmc));
if (!mmc)
ret = -ENOMEM;
memset(mmc, 0, sizeof(*mmc));
host = malloc(sizeof(struct sh_mmcif_host));
if (!host)
ret = -ENOMEM;
memset(host, 0, sizeof(*host));
mmc->f_min = CLKDEV_MMC_INIT;
mmc->f_max = CLKDEV_EMMC_DATA;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
MMC_MODE_8BIT;
memcpy(mmc->name, DRIVER_NAME, sizeof(DRIVER_NAME));
mmc->send_cmd = sh_mmcif_request;
mmc->set_ios = sh_mmcif_set_ios;
mmc->init = sh_mmcif_init;
mmc->getcd = NULL;
host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
host->clk = CONFIG_SH_MMCIF_CLK;
mmc->priv = host;
mmc_register(mmc);
return ret;
}
static int s3c64x0_mmc_initialize(int dev_index)
{
struct mmc *mmc;
mmc = &mmc_dev[dev_index];
sprintf(mmc->name, "SAMSUNG SD/MMC");
mmc->priv = &mmc_host[dev_index];
mmc->send_cmd = mmc_send_cmd;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_core_init;
mmc->detect_mmc = mmc_card_detect;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
mmc->f_min = 400000;
mmc->f_max = 52000000;
mmc_host[dev_index].clock = 0;
mmc_host[dev_index].reg = s3c64x0_get_base_mmc(dev_index);
mmc_register(mmc);
return 0;
}
struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode)
{
struct mmc *mmc;
mmc = malloc(sizeof(*mmc));
if (!mmc)
return NULL;
memset(mmc, 0, sizeof(*mmc));
mmc->priv = spi_setup_slave(bus, cs, speed, mode);
if (!mmc->priv) {
free(mmc);
return NULL;
}
sprintf(mmc->name, "MMC_SPI");
mmc->send_cmd = mmc_spi_request;
mmc->set_ios = mmc_spi_set_ios;
mmc->init = mmc_spi_init_p;
mmc->getcd = NULL;
mmc->host_caps = MMC_MODE_SPI;
mmc->voltages = MMC_SPI_VOLTAGE;
mmc->f_max = speed;
mmc->f_min = MMC_SPI_MIN_CLOCK;
mmc->block_dev.part_type = PART_TYPE_DOS;
mmc_register(mmc);
return mmc;
}
int bfin_mmc_init(bd_t *bis)
{
struct mmc *mmc = NULL;
mmc = malloc(sizeof(struct mmc));
if (!mmc)
return -ENOMEM;
sprintf(mmc->name, "Blackfin SDH");
mmc->send_cmd = bfin_sdh_request;
mmc->set_ios = bfin_sdh_set_ios;
mmc->init = bfin_sdh_init;
mmc->getcd = NULL;
mmc->host_caps = MMC_MODE_4BIT;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->f_max = get_sclk();
mmc->f_min = mmc->f_max >> 9;
mmc->b_max = 1;
mmc_register(mmc);
return 0;
}
static int s5p_mmc_initialize(int dev_index, int bus_width)
{
struct mmc *mmc;
mmc = &mmc_dev[dev_index];
sprintf(mmc->name, "SAMSUNG SD/MMC");
mmc->priv = &mmc_host[dev_index];
mmc->send_cmd = mmc_send_cmd;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_core_init;
mmc->getcd = NULL;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
if (bus_width == 8)
mmc->host_caps = MMC_MODE_8BIT;
else
mmc->host_caps = MMC_MODE_4BIT;
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
mmc->f_min = 400000;
mmc->f_max = 52000000;
mmc_host[dev_index].dev_index = dev_index;
mmc_host[dev_index].clock = 0;
mmc_host[dev_index].reg = s5p_get_base_mmc(dev_index);
mmc->b_max = 0;
mmc_register(mmc);
return 0;
}
// #define CONFIG_TSD 1
static void board_mmc_register(unsigned port)
{
struct aml_card_sd_info *aml_priv=cpu_sdio_get(port);
struct mmc *mmc = (struct mmc *)malloc(sizeof(struct mmc));
if(aml_priv==NULL||mmc==NULL)
return;
memset(mmc,0,sizeof(*mmc));
aml_priv->sdio_init=sdio_init;
aml_priv->sdio_detect=sdio_detect;
aml_priv->sdio_pwr_off=sdio_pwr_off;
aml_priv->sdio_pwr_on=sdio_pwr_on;
aml_priv->sdio_pwr_prepare=sdio_pwr_prepare;
// #ifdef CONFIG_TSD
// // if(mmc->block_dev.dev > 0)//tsd
// mmc->block_dev.if_type = IF_TYPE_SD;
// #else
// // if(mmc->block_dev.dev > 0)//emmc
// mmc->block_dev.if_type = IF_TYPE_MMC;
// #endif
sdio_register(mmc, aml_priv);
#if 0
strncpy(mmc->name,aml_priv->name,31);
mmc->priv = aml_priv;
aml_priv->removed_flag = 1;
aml_priv->inited_flag = 0;
aml_priv->sdio_init=sdio_init;
aml_priv->sdio_detect=sdio_detect;
aml_priv->sdio_pwr_off=sdio_pwr_off;
aml_priv->sdio_pwr_on=sdio_pwr_on;
aml_priv->sdio_pwr_prepare=sdio_pwr_prepare;
mmc->send_cmd = aml_sd_send_cmd;
mmc->set_ios = aml_sd_cfg_swth;
mmc->init = aml_sd_init;
mmc->rca = 1;
mmc->voltages = MMC_VDD_33_34;
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS;
//mmc->host_caps = MMC_MODE_4BIT;
mmc->bus_width = 1;
mmc->clock = 300000;
mmc->f_min = 200000;
mmc->f_max = 50000000;
mmc_register(mmc);
#endif
}
int omap_mmc_init(int dev_index)
{
struct mmc *mmc;
mmc = &hsmmc_dev[dev_index];
sprintf(mmc->name, "OMAP SD/MMC");
mmc->send_cmd = mmc_send_cmd;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_init_setup;
switch (dev_index) {
case 0:
mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE;
break;
case 1:
mmc->priv = (hsmmc_t *)OMAP_HSMMC2_BASE;
break;
case 2:
mmc->priv = (hsmmc_t *)OMAP_HSMMC3_BASE;
break;
default:
mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE;
return 1;
}
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
mmc->f_min = 400000;
mmc->f_max = 52000000;
mmc->b_max = 0;
#if defined(CONFIG_OMAP34XX)
/*
* Silicon revs 2.1 and older do not support multiblock transfers.
*/
if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
mmc->b_max = 1;
#endif
mmc_register(mmc);
return 0;
}
static void register_mmc_device(struct mmc *dev)
{
copy_id(dev->name, sizeof(dev->name), "Sandbox MMC");
dev->priv = &mmc_host;
dev->send_cmd = sandbox_mmc_send_cmd;
dev->set_ios = sandbox_mmc_set_ios;
dev->init = sandbox_mmc_core_init;
dev->getcd = sandbox_mmc_getcd;
/* These following values taken from the regular mmc driver. */
dev->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
dev->host_caps = MMC_MODE_8BIT;
dev->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
dev->f_min = 375000;
dev->f_max = 48000000;
dev->b_max = 0;
mmc_register(dev);
}
void sdio_register(struct mmc* mmc,struct aml_card_sd_info * aml_priv)
{
#ifdef CONFIG_STORE_COMPATIBLE
int card_type;
#endif
strncpy(mmc->name,aml_priv->name,31);
mmc->priv = aml_priv;
aml_priv->removed_flag = 1;
aml_priv->inited_flag = 0;
/*
aml_priv->sdio_init=sdio_init;
aml_priv->sdio_detect=sdio_detect;
aml_priv->sdio_pwr_off=sdio_pwr_off;
aml_priv->sdio_pwr_on=sdio_pwr_on;
aml_priv->sdio_pwr_prepare=sdio_pwr_prepare;
*/
mmc->send_cmd = aml_sd_send_cmd;
mmc->set_ios = aml_sd_cfg_swth;
mmc->init = aml_sd_init;
mmc->rca = 1;
mmc->voltages = MMC_VDD_33_34;
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS;
//mmc->host_caps = MMC_MODE_4BIT;
mmc->bus_width = 1;
mmc->clock = 300000;
mmc->f_min = 200000;
mmc->f_max = 50000000;
mmc->is_inited = false;
mmc_register(mmc);
//WRITE_CBUS_REG(RESET6_REGISTER, (1<<8));
WRITE_CBUS_REG(SDIO_AHB_CBUS_CTRL, 0);
#ifdef CONFIG_STORE_COMPATIBLE
card_type = AML_GET_CARD_TYPE(aml_card_type, aml_priv->sdio_port);
if (card_type == CARD_TYPE_MMC)
mmc->block_dev.if_type = IF_TYPE_MMC;
else
mmc->block_dev.if_type = IF_TYPE_SD;
// printf("\033[0;40;32m [%s] port=%d, aml_card_type=%#x, card_type=%d, mmc->block_dev.if_type=%d \033[0m\n",
// __FUNCTION__, aml_priv->sdio_port, aml_card_type, card_type, mmc->block_dev.if_type);
#endif
}
static int s3c_hsmmc_initialize(int channel)
{
struct mmc *mmc;
mmc = &mmc_channel[channel];
sprintf(mmc->name, "S3C_HSMMC%d", channel);
mmc->priv = &mmc_host[channel];
mmc->send_cmd = s3c_hsmmc_send_command;
mmc->set_ios = s3c_hsmmc_set_ios;
mmc->init = s3c_hsmmc_init;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT |
MMC_MODE_HS_52MHz | MMC_MODE_HS;
mmc->f_min = 400000;
mmc->f_max = 52000000;
mmc_host[channel].clock = 0;
switch(channel) {
case 0:
mmc_host[channel].ioaddr = (void *)ELFIN_HSMMC_0_BASE;
break;
case 1:
mmc_host[channel].ioaddr = (void *)ELFIN_HSMMC_1_BASE;
break;
case 2:
mmc_host[channel].ioaddr = (void *)ELFIN_HSMMC_2_BASE;
break;
#ifdef USE_MMC3
case 3:
mmc_host[channel].ioaddr = (void *)ELFIN_HSMMC_3_BASE;
break;
#endif
default:
printk("mmc err: not supported channel %d\n", channel);
}
return mmc_register(mmc);
}
int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
{
struct mmc *mmc;
int err = 0;
mmc = malloc(sizeof(struct mmc));
if (!mmc) {
printf("mmc malloc fail!\n");
return -1;
}
mmc->priv = host;
host->mmc = mmc;
sprintf(mmc->name, "%s", host->name);
mmc->send_cmd = dwmci_send_cmd;
mmc->set_ios = dwmci_set_ios;
mmc->init = dwmci_init;
mmc->f_min = min_clk;
mmc->f_max = max_clk;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
mmc->host_caps = host->caps;
if (host->buswidth == 8) {
mmc->host_caps |= MMC_MODE_8BIT;
mmc->host_caps &= ~MMC_MODE_4BIT;
} else {
mmc->host_caps |= MMC_MODE_4BIT;
mmc->host_caps &= ~MMC_MODE_8BIT;
}
mmc->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;
err = mmc_register(mmc);
return err;
}
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mmc *mmc = NULL;
struct mxsmmc_priv *priv = NULL;
int ret;
mmc = malloc(sizeof(struct mmc));
if (!mmc)
return -ENOMEM;
priv = malloc(sizeof(struct mxsmmc_priv));
if (!priv) {
free(mmc);
return -ENOMEM;
}
priv->desc = mxs_dma_desc_alloc();
if (!priv->desc) {
free(priv);
free(mmc);
return -ENOMEM;
}
ret = mxs_dma_init_channel(id);
if (ret)
return ret;
priv->mmc_is_wp = wp;
priv->id = id;
switch (id) {
case 0:
priv->regs = (struct mxs_ssp_regs *)MXS_SSP0_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0;
break;
case 1:
priv->regs = (struct mxs_ssp_regs *)MXS_SSP1_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1;
break;
case 2:
priv->regs = (struct mxs_ssp_regs *)MXS_SSP2_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2;
break;
case 3:
priv->regs = (struct mxs_ssp_regs *)MXS_SSP3_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3;
break;
}
sprintf(mmc->name, "MXS MMC");
mmc->send_cmd = mxsmmc_send_cmd;
mmc->set_ios = mxsmmc_set_ios;
mmc->init = mxsmmc_init;
mmc->getcd = NULL;
mmc->priv = priv;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
MMC_MODE_HS_52MHz | MMC_MODE_HS;
/*
* SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
* SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
* CLOCK_DIVIDE has to be an even value from 2 to 254, and
* CLOCK_RATE could be any integer from 0 to 255.
*/
mmc->f_min = 400000;
mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2;
mmc->b_max = 0x20;
mmc_register(mmc);
return 0;
}
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
{
struct mmc *mmc = NULL;
struct mxsmmc_priv *priv = NULL;
int ret;
#if defined(CONFIG_MX23)
const unsigned int mxsmmc_max_id = 2;
const unsigned int mxsmmc_clk_id = 0;
#elif defined(CONFIG_MX28)
const unsigned int mxsmmc_max_id = 4;
const unsigned int mxsmmc_clk_id = id;
#endif
if (id >= mxsmmc_max_id)
return -ENODEV;
mmc = malloc(sizeof(struct mmc));
if (!mmc)
return -ENOMEM;
priv = malloc(sizeof(struct mxsmmc_priv));
if (!priv) {
free(mmc);
return -ENOMEM;
}
priv->desc = mxs_dma_desc_alloc();
if (!priv->desc) {
free(priv);
free(mmc);
return -ENOMEM;
}
ret = mxs_dma_init_channel(id + mxsmmc_id_offset);
if (ret)
return ret;
priv->mmc_is_wp = wp;
priv->mmc_cd = cd;
priv->id = id;
priv->regs = mxs_ssp_regs_by_bus(id);
sprintf(mmc->name, "MXS MMC");
mmc->send_cmd = mxsmmc_send_cmd;
mmc->set_ios = mxsmmc_set_ios;
mmc->init = mxsmmc_init;
mmc->getcd = NULL;
mmc->priv = priv;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
MMC_MODE_HS_52MHz | MMC_MODE_HS;
/*
* SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
* SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
* CLOCK_DIVIDE has to be an even value from 2 to 254, and
* CLOCK_RATE could be any integer from 0 to 255.
*/
mmc->f_min = 400000;
mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
mmc->b_max = 0x20;
mmc_register(mmc);
return 0;
}
int omap_mmc_init(int dev_index)
{
struct mmc *mmc;
mmc = &hsmmc_dev[dev_index];
if (dev_index == 1)
sprintf(mmc->name, "ON-BOARD SDIO");
else
sprintf(mmc->name, "OMAP SD/MMC");
mmc->send_cmd = mmc_send_cmd;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_init_setup;
#if !defined(CONFIG_TI81XX)
switch (dev_index) {
case 0:
mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE;
break;
case 1:
mmc->priv = (hsmmc_t *)OMAP_HSMMC2_BASE;
break;
case 2:
mmc->priv = (hsmmc_t *)OMAP_HSMMC3_BASE;
break;
default:
mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE;
return 1;
}
#else
switch (dev_index) {
case 0:
mmc->priv = (hsmmc_t *)OMAP_HSMMC_BASE;
break;
case 1:
mmc->priv = (hsmmc_t *)OMAP_SDIO_BASE;
break;
default:
mmc->priv = (hsmmc_t *)OMAP_HSMMC_BASE;
return 1;
}
#endif
if(dev_index == 1)
{
mmc->voltages = MMC_VDD_29_30 | MMC_VDD_165_195;
mmc->host_caps = 0;
} else {
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
}
mmc->f_min = 400000;
if(dev_index == 1)
mmc->f_max = 24000000;
else
mmc->f_max = 52000000;
mmc_register(mmc);
return 0;
}
int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
{
struct mmc_host *host;
char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
struct mmc *mmc;
debug(" tegra2_mmc_init: index %d, bus width %d "
"pwr_gpio %d cd_gpio %d\n",
dev_index, bus_width, pwr_gpio, cd_gpio);
host = &mmc_host[dev_index];
host->clock = 0;
host->pwr_gpio = pwr_gpio;
host->cd_gpio = cd_gpio;
tegra2_get_setup(host, dev_index);
clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
if (host->pwr_gpio >= 0) {
sprintf(gpusage, "SD/MMC%d PWR", dev_index);
gpio_request(host->pwr_gpio, gpusage);
gpio_direction_output(host->pwr_gpio, 1);
}
if (host->cd_gpio >= 0) {
sprintf(gpusage, "SD/MMC%d CD", dev_index);
gpio_request(host->cd_gpio, gpusage);
gpio_direction_input(host->cd_gpio);
}
mmc = &mmc_dev[dev_index];
sprintf(mmc->name, "Tegra2 SD/MMC");
mmc->priv = host;
mmc->send_cmd = mmc_send_cmd;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_core_init;
mmc->getcd = tegra2_mmc_getcd;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
if (bus_width == 8)
mmc->host_caps = MMC_MODE_8BIT;
else
mmc->host_caps = MMC_MODE_4BIT;
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
/*
* min freq is for card identification, and is the highest
* low-speed SDIO card frequency (actually 400KHz)
* max freq is highest HS eMMC clock as per the SD/MMC spec
* (actually 52MHz)
* Both of these are the closest equivalents w/216MHz source
* clock and Tegra2 SDMMC divisors.
*/
mmc->f_min = 375000;
mmc->f_max = 48000000;
mmc_register(mmc);
return 0;
}
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
int wp_gpio)
{
struct mmc *mmc = &hsmmc_dev[dev_index];
struct omap_hsmmc_data *priv_data = &hsmmc_dev_data[dev_index];
uint host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
MMC_MODE_HC;
sprintf(mmc->name, "OMAP SD/MMC");
mmc->send_cmd = mmc_send_cmd;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_init_setup;
mmc->priv = priv_data;
switch (dev_index) {
case 0:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
break;
#ifdef OMAP_HSMMC2_BASE
case 1:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
defined(CONFIG_DRA7XX)) && defined(CONFIG_HSMMC2_8BIT)
/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
break;
#endif
#ifdef OMAP_HSMMC3_BASE
case 2:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
/* Enable 8-bit interface for eMMC on DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
break;
#endif
default:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
return 1;
}
priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
if (priv_data->cd_gpio != -1)
mmc->getcd = omap_mmc_getcd;
priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
if (priv_data->wp_gpio != -1)
mmc->getwp = omap_mmc_getwp;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
mmc->host_caps = host_caps_val & ~host_caps_mask;
mmc->f_min = 400000;
if (f_max != 0)
mmc->f_max = f_max;
else {
if (mmc->host_caps & MMC_MODE_HS) {
if (mmc->host_caps & MMC_MODE_HS_52MHz)
mmc->f_max = 52000000;
else
mmc->f_max = 26000000;
} else
mmc->f_max = 20000000;
}
mmc->b_max = 0;
#if defined(CONFIG_OMAP34XX)
/*
* Silicon revs 2.1 and older do not support multiblock transfers.
*/
if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
mmc->b_max = 1;
#endif
mmc_register(mmc);
return 0;
}
