static unsigned long wandboard_dram_init(void)
{
int cpu_type = __imx6_cpu_type();
unsigned long memsize;
switch (cpu_type) {
case IMX6_CPUTYPE_IMX6S:
mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
memsize = SZ_512M;
break;
case IMX6_CPUTYPE_IMX6DL:
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
memsize = SZ_1G;
break;
case IMX6_CPUTYPE_IMX6Q:
mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
memsize = SZ_2G;
break;
default:
return 0;
}
__udelay(100);
mmdc_do_write_level_calibration();
mmdc_do_dqs_calibration();
#ifdef DEBUG
mmdc_print_calibration_results();
#endif
return memsize;
}
/*
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM
* - no variable global data is available
*/
void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
gpr_init();
/* setup GP timer */
timer_init();
#ifdef CONFIG_BOARD_POSTCLK_INIT
board_postclk_init();
#endif
#ifdef CONFIG_FSL_ESDHC
get_clocks();
#endif
/* Setup IOMUX and configure basics. */
novena_spl_setup_iomux_audio();
novena_spl_setup_iomux_buttons();
novena_spl_setup_iomux_enet();
novena_spl_setup_iomux_fpga();
novena_spl_setup_iomux_i2c();
novena_spl_setup_iomux_pcie();
novena_spl_setup_iomux_sdhc();
novena_spl_setup_iomux_spi();
novena_spl_setup_iomux_uart();
novena_spl_setup_iomux_video();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* Start the DDR DRAM */
mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs);
mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600);
/* Perform DDR DRAM calibration */
udelay(100);
mmdc_do_write_level_calibration();
mmdc_do_dqs_calibration();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
{
int ret;
/* Perform DDR DRAM calibration */
udelay(100);
ret = mmdc_do_write_level_calibration(sysinfo);
if (ret) {
printf("DDR: Write level calibration error [%d]\n", ret);
return;
}
ret = mmdc_do_dqs_calibration(sysinfo);
if (ret) {
printf("DDR: DQS calibration error [%d]\n", ret);
return;
}
spl_dram_print_cal(sysinfo);
}
ENTRY_FUNCTION(start_imx6_realq7, r0, r1, r2)
{
unsigned long sdram = 0x10000000;
void *fdt;
arm_cpu_lowlevel_init();
arm_setup_stack(0x00940000 - 8);
fdt = __dtb_imx6q_dmo_edmqmx6_start - get_runtime_offset();
if (get_pc() < 0x10000000) {
sdram_init();
mmdc_do_write_level_calibration();
mmdc_do_dqs_calibration();
}
barebox_arm_entry(sdram, SZ_2G, fdt);
}
/*
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM
* - no variable global data is available
*/
void board_init_f(ulong dummy)
{
int errs;
struct mx6_mmdc_calibration calibration = {0};
memset((void *)gd, 0, sizeof(struct global_data));
/* write leveling calibration defaults */
calibration.p0_mpwrdlctl = 0x40404040;
calibration.p1_mpwrdlctl = 0x40404040;
/* setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
SETUP_IOMUX_PADS(uart_pads);
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
if (sysinfo.dsize != 1) {
if (is_cpu_type(MXC_CPU_MX6SX) ||
is_cpu_type(MXC_CPU_MX6UL) ||
is_cpu_type(MXC_CPU_MX6ULL) ||
is_cpu_type(MXC_CPU_MX6SL)) {
printf("cpu type 0x%x doesn't support 64-bit bus\n",
get_cpu_type());
reset_cpu(0);
}
}
#ifdef CONFIG_MX6SL
mx6sl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sl_ddr_ioregs,
&mx6sl_grp_ioregs);
#else
if (is_cpu_type(MXC_CPU_MX6Q)) {
mx6dq_dram_iocfg(CONFIG_DDRWIDTH, &mx6dq_ddr_ioregs,
&mx6dq_grp_ioregs);
} else {
mx6sdl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sdl_ddr_ioregs,
&mx6sdl_grp_ioregs);
}
#endif
mx6_dram_cfg(&sysinfo, &calibration, &ddrtype);
errs = mmdc_do_write_level_calibration(&sysinfo);
if (errs) {
printf("error %d from write level calibration\n", errs);
} else {
errs = mmdc_do_dqs_calibration(&sysinfo);
if (errs) {
printf("error %d from dqs calibration\n", errs);
} else {
printf("completed successfully\n");
mmdc_read_calibration(&sysinfo, &calibration);
display_calibration(&calibration);
}
}
}
