static WORD mmu_read_word(LONG addr) { return (mmu_read_byte(addr)<<8)|mmu_read_byte(addr+1); }
static void mac_write (struct device_desc *dev) { struct device_interrupt *intr = &dev->intr; struct net_device *net_dev = (struct net_device *) dev->dev; struct net_s3c4510b_io *io = (struct net_s3c4510b_io *) dev->data; struct machine_config *mc = (struct machine_config *) dev->mach; ARMul_State *state = (ARMul_State *) mc->state; fault_t fault; u32 ptr, status, len; int i; fault = mmu_read_word (state, io->bdmatxptr, &ptr); /* if( fault ) { *addr = io->bdmatxptr; return fault; } */ if (!(ptr & BDMA_owner)) return; ptr &= ~BDMA_owner; fault = mmu_read_word (state, io->bdmatxptr + 8, &len); /* if( fault ) { *addr = io->bdmatxptr + 8; return fault; } */ len &= 0xffff; if (len > sizeof (io->mac_buf)) return; for (i = 0; i < len; i++) { fault = mmu_read_byte (state, ptr + i, io->mac_buf + i); /* if( fault ) { *addr = ptr + i; return fault; } */ } //Update TXstatus status = len | (Comp << 16); fault = mmu_write_word (state, io->bdmatxptr + 8, status); //print_packet(io->mac_buf, len); /* if( fault ) { *addr = io->bdmatxptr + 8; return fault; } */ //set owner bit of desc to CPU fault = mmu_write_word (state, io->bdmatxptr, ptr); /* if( fault ) { *addr = io->bdmatxptr; return fault; } */ //get next desc fault = mmu_read_word (state, io->bdmatxptr + 12, &io->bdmatxptr); /* if( fault ) { *addr = io->bdmatxptr + 12; */ net_dev->net_write (net_dev, io->mac_buf, len); //write( skyeye_config.net[0].fd, io->mac_buf, len ); //trigger interrupt if (io->mactxcon & EnComp) { mc->mach_set_intr (intr->interrupts[INT_S3C4510B_MACTX]); mc->mach_update_intr (mc); //s3c4510b_set_interrupt(INT_MACTX); //s3c4510b_update_int(state); } }