asmlinkage void __init processor_init(void) { int loop; for (loop = 0x000; loop < 0x400; loop += 8) __set_intr_stub(loop, __common_exception); __set_intr_stub(EXCEP_ITLBMISS, itlb_miss); __set_intr_stub(EXCEP_DTLBMISS, dtlb_miss); __set_intr_stub(EXCEP_IAERROR, itlb_aerror); __set_intr_stub(EXCEP_DAERROR, dtlb_aerror); __set_intr_stub(EXCEP_BUSERROR, raw_bus_error); __set_intr_stub(EXCEP_DOUBLE_FAULT, double_fault); __set_intr_stub(EXCEP_FPU_DISABLED, fpu_disabled); __set_intr_stub(EXCEP_SYSCALL0, system_call); __set_intr_stub(EXCEP_NMI, nmi_handler); __set_intr_stub(EXCEP_WDT, nmi_handler); __set_intr_stub(EXCEP_IRQ_LEVEL0, irq_handler); __set_intr_stub(EXCEP_IRQ_LEVEL1, irq_handler); __set_intr_stub(EXCEP_IRQ_LEVEL2, irq_handler); __set_intr_stub(EXCEP_IRQ_LEVEL3, irq_handler); __set_intr_stub(EXCEP_IRQ_LEVEL4, irq_handler); __set_intr_stub(EXCEP_IRQ_LEVEL5, irq_handler); __set_intr_stub(EXCEP_IRQ_LEVEL6, irq_handler); IVAR0 = EXCEP_IRQ_LEVEL0; IVAR1 = EXCEP_IRQ_LEVEL1; IVAR2 = EXCEP_IRQ_LEVEL2; IVAR3 = EXCEP_IRQ_LEVEL3; IVAR4 = EXCEP_IRQ_LEVEL4; IVAR5 = EXCEP_IRQ_LEVEL5; IVAR6 = EXCEP_IRQ_LEVEL6; mn10300_dcache_flush_inv(); mn10300_icache_inv(); for (loop = 0; loop < NR_IRQS; loop++) GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; TM0MD = 0; TM1MD = 0; TM2MD = 0; TM3MD = 0; TM4MD = 0; TM5MD = 0; TM6MD = 0; TM6MDA = 0; TM6MDB = 0; TM7MD = 0; TM8MD = 0; TM9MD = 0; TM10MD = 0; TM11MD = 0; calibrate_clock(); }
/** * flush_icache_range - Globally flush dcache and invalidate icache for region * @start: The starting virtual address of the region. * @end: The ending virtual address of the region. * * This is used by the kernel to globally flush some code it has just written * from the dcache back to RAM and then to globally invalidate the icache over * that region so that that code can be run on all CPUs in the system. */ void flush_icache_range(unsigned long start, unsigned long end) { unsigned long start_page, end_page; unsigned long flags; flags = smp_lock_cache(); if (end > 0x80000000UL) { /* addresses above 0xa0000000 do not go through the cache */ if (end > 0xa0000000UL) { end = 0xa0000000UL; if (start >= end) goto done; } /* kernel addresses between 0x80000000 and 0x9fffffff do not * require page tables, so we just map such addresses * directly */ start_page = (start >= 0x80000000UL) ? start : 0x80000000UL; mn10300_local_dcache_flush_range(start_page, end); mn10300_local_icache_inv_range(start_page, end); smp_cache_call(SMP_IDCACHE_INV_FLUSH_RANGE, start_page, end); if (start_page == start) goto done; end = start_page; } start_page = start & PAGE_MASK; end_page = (end - 1) & PAGE_MASK; if (start_page == end_page) { /* the first and last bytes are on the same page */ flush_icache_page_range(start, end); } else if (start_page + 1 == end_page) { /* split over two virtually contiguous pages */ flush_icache_page_range(start, end_page); flush_icache_page_range(end_page, end); } else { /* more than 2 pages; just flush the entire cache */ mn10300_dcache_flush(); mn10300_icache_inv(); smp_cache_call(SMP_IDCACHE_INV_FLUSH, 0, 0); } done: smp_unlock_cache(flags); }
void flush_icache_range(unsigned long start, unsigned long end) { unsigned long start_page, end_page; unsigned long flags; flags = smp_lock_cache(); if (end > 0x80000000UL) { /* */ if (end > 0xa0000000UL) { end = 0xa0000000UL; if (start >= end) goto done; } /* */ start_page = (start >= 0x80000000UL) ? start : 0x80000000UL; mn10300_local_dcache_flush_range(start_page, end); mn10300_local_icache_inv_range(start_page, end); smp_cache_call(SMP_IDCACHE_INV_FLUSH_RANGE, start_page, end); if (start_page == start) goto done; end = start_page; } start_page = start & PAGE_MASK; end_page = (end - 1) & PAGE_MASK; if (start_page == end_page) { /* */ flush_icache_page_range(start, end); } else if (start_page + 1 == end_page) { /* */ flush_icache_page_range(start, end_page); flush_icache_page_range(end_page, end); } else { /* */ mn10300_dcache_flush(); mn10300_icache_inv(); smp_cache_call(SMP_IDCACHE_INV_FLUSH, 0, 0); } done: smp_unlock_cache(flags); }
/* * initialise the on-silicon processor peripherals */ asmlinkage void __init processor_init(void) { int loop; /* set up the exception table first */ for (loop = 0x000; loop < 0x400; loop += 8) __set_intr_stub(loop, __common_exception); __set_intr_stub(EXCEP_ITLBMISS, itlb_miss); __set_intr_stub(EXCEP_DTLBMISS, dtlb_miss); __set_intr_stub(EXCEP_IAERROR, itlb_aerror); __set_intr_stub(EXCEP_DAERROR, dtlb_aerror); __set_intr_stub(EXCEP_BUSERROR, raw_bus_error); __set_intr_stub(EXCEP_DOUBLE_FAULT, double_fault); __set_intr_stub(EXCEP_FPU_DISABLED, fpu_disabled); __set_intr_stub(EXCEP_SYSCALL0, system_call); __set_intr_stub(EXCEP_NMI, nmi_handler); __set_intr_stub(EXCEP_WDT, nmi_handler); __set_intr_stub(EXCEP_IRQ_LEVEL0, irq_handler); __set_intr_stub(EXCEP_IRQ_LEVEL1, irq_handler); __set_intr_stub(EXCEP_IRQ_LEVEL2, irq_handler); __set_intr_stub(EXCEP_IRQ_LEVEL3, irq_handler); __set_intr_stub(EXCEP_IRQ_LEVEL4, irq_handler); __set_intr_stub(EXCEP_IRQ_LEVEL5, irq_handler); __set_intr_stub(EXCEP_IRQ_LEVEL6, irq_handler); IVAR0 = EXCEP_IRQ_LEVEL0; IVAR1 = EXCEP_IRQ_LEVEL1; IVAR2 = EXCEP_IRQ_LEVEL2; IVAR3 = EXCEP_IRQ_LEVEL3; IVAR4 = EXCEP_IRQ_LEVEL4; IVAR5 = EXCEP_IRQ_LEVEL5; IVAR6 = EXCEP_IRQ_LEVEL6; #ifndef CONFIG_MN10300_HAS_CACHE_SNOOP mn10300_dcache_flush_inv(); mn10300_icache_inv(); #endif /* disable all interrupts and set to priority 6 (lowest) */ #ifdef CONFIG_SMP for (loop = 0; loop < GxICR_NUM_IRQS; loop++) GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; #else /* !CONFIG_SMP */ for (loop = 0; loop < NR_IRQS; loop++) GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; #endif /* !CONFIG_SMP */ /* clear the timers */ TM0MD = 0; TM1MD = 0; TM2MD = 0; TM3MD = 0; TM4MD = 0; TM5MD = 0; TM6MD = 0; TM6MDA = 0; TM6MDB = 0; TM7MD = 0; TM8MD = 0; TM9MD = 0; TM10MD = 0; TM11MD = 0; TM12MD = 0; TM13MD = 0; TM14MD = 0; TM15MD = 0; calibrate_clock(); }