/**
* \todo Check for LSE good timeout and return with -1,
* possible ISR optimization? or at least ISR should be cough in case of failure
*/
void stm32_rcc_enablelse(void)
{
/* Enable LSE */
modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON);
/* We could wait for ISR here ... */
while( !(getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) ) up_waste();
/* Select LSE as RTC Clock Source */
modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE);
/* Enable Clock */
modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
}
void stm32_rcc_enablelse(void)
{
/* The LSE is in the RTC domain and write access is denied to this domain
* after reset, you have to enable write access using DBP bit in the PWR CR
* register before to configuring the LSE.
*/
stm32_pwr_enablebkp(true);
#if defined(CONFIG_STM32_STM32L15XX)
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit
* the RCC CSR register.
*/
modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSEON);
/* Wait for the LSE clock to be ready */
while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSERDY) == 0)
{
up_waste();
}
#else
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit
* the RCC BDCR register.
*/
modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON);
/* Wait for the LSE clock to be ready */
while ((getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) == 0)
{
up_waste();
}
#endif
/* Disable backup domain access if it was disabled on entry */
stm32_pwr_enablebkp(false);
}
static inline void stm32_modifyreg16(FAR const struct stm32_cap_priv_s *priv,
uint8_t offset, uint16_t clearbits,
uint16_t setbits)
{
modifyreg16(priv->base + offset, clearbits, setbits);
}
static void init_lcd_backlight(void)
{
uint16_t ccmr;
uint16_t ccer;
/* Configure PB5 as TIM3 CH2 output */
stm32_configgpio(GPIO_TIM3_CH2OUT);
/* Enable timer 3 clocking */
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN);
/* Reset timer 3 */
modifyreg32(STM32_RCC_APB1RSTR, 0, RCC_APB1RSTR_TIM3RST);
modifyreg32(STM32_RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST, 0);
/* Reset the Counter Mode and set the clock division */
putreg16(0, STM32_TIM3_CR1);
/* Set the Autoreload value */
putreg16(LCD_BL_TIMER_PERIOD, STM32_TIM3_ARR);
/* Set the Prescaler value */
putreg16(0, STM32_TIM3_PSC);
/* Generate an update event to reload the Prescaler value immediatly */
putreg16(ATIM_EGR_UG, STM32_TIM3_EGR);
/* Disable the Channel 2 */
ccer = getreg16(STM32_TIM3_CCER);
ccer &= ~ATIM_CCER_CC2E;
putreg16(ccer, STM32_TIM3_CCER);
/* Select the Output Compare Mode Bits */
ccmr = getreg16(STM32_TIM3_CCMR1);
ccmr &= ATIM_CCMR1_OC2M_MASK;
ccmr |= (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT);
putreg16(0, STM32_TIM3_CCR2);
/* Select the output polarity level == HIGH */
ccer &= !ATIM_CCER_CC2P;
/* Enable channel 2*/
ccer |= ATIM_CCER_CC2E;
/* Write the timer configuration */
putreg16(ccmr, STM32_TIM3_CCMR1);
putreg16(ccer, STM32_TIM3_CCER);
/* Set the auto preload enable bit */
modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_ARPE);
/* Enable Backlight Timer !!!!*/
modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_CEN);
/* Dump timer3 registers */
lcddbg("APB1ENR: %08x\n", getreg32(STM32_RCC_APB1ENR));
lcddbg("CR1: %04x\n", getreg32(STM32_TIM3_CR1));
lcddbg("CR2: %04x\n", getreg32(STM32_TIM3_CR2));
lcddbg("SMCR: %04x\n", getreg32(STM32_TIM3_SMCR));
lcddbg("DIER: %04x\n", getreg32(STM32_TIM3_DIER));
lcddbg("SR: %04x\n", getreg32(STM32_TIM3_SR));
lcddbg("EGR: %04x\n", getreg32(STM32_TIM3_EGR));
lcddbg("CCMR1: %04x\n", getreg32(STM32_TIM3_CCMR1));
lcddbg("CCMR2: %04x\n", getreg32(STM32_TIM3_CCMR2));
lcddbg("CCER: %04x\n", getreg32(STM32_TIM3_CCER));
lcddbg("CNT: %04x\n", getreg32(STM32_TIM3_CNT));
lcddbg("PSC: %04x\n", getreg32(STM32_TIM3_PSC));
lcddbg("ARR: %04x\n", getreg32(STM32_TIM3_ARR));
lcddbg("CCR1: %04x\n", getreg32(STM32_TIM3_CCR1));
lcddbg("CCR2: %04x\n", getreg32(STM32_TIM3_CCR2));
lcddbg("CCR3: %04x\n", getreg32(STM32_TIM3_CCR3));
lcddbg("CCR4: %04x\n", getreg32(STM32_TIM3_CCR4));
lcddbg("CCR4: %04x\n", getreg32(STM32_TIM3_CCR4));
lcddbg("CCR4: %04x\n", getreg32(STM32_TIM3_CCR4));
lcddbg("DMAR: %04x\n", getreg32(STM32_TIM3_DMAR));
}
/** Modify register value by offset */
static inline void stm32_tim_modifyreg(FAR struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits)
{
modifyreg16( ((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits);
}
void stm32_flash_lock(void)
{
modifyreg16(STM32_FLASH_CR, 0, FLASH_CR_LOCK);
}
