Esempio n. 1
0
void genmov_s()
{
#ifdef INTERPRET_MOV_S
   gencallinterp((u32)MOV_S, 0);
#else
   gencheck_cop1_unusable();
   mov_eax_memoffs32((u32 *)(&reg_cop1_simple[dst->f.cf.fs]));
   mov_reg32_preg32(EBX, EAX);
   mov_eax_memoffs32((u32 *)(&reg_cop1_simple[dst->f.cf.fd]));
   mov_preg32_reg32(EAX, EBX);
#endif
}
Esempio n. 2
0
void genmov_s(void)
{
#ifdef INTERPRET_MOV_S
   gencallinterp((unsigned int)cached_interpreter_table.MOV_S, 0);
#else
   gencheck_cop1_unusable();
   mov_eax_memoffs32((unsigned int *)(&reg_cop1_simple[dst->f.cf.fs]));
   mov_reg32_preg32(EBX, EAX);
   mov_eax_memoffs32((unsigned int *)(&reg_cop1_simple[dst->f.cf.fd]));
   mov_preg32_reg32(EAX, EBX);
#endif
}
Esempio n. 3
0
void gendmfc1(void)
{
#ifdef INTERPRET_DMFC1
   gencallinterp((unsigned int)DMFC1, 0);
#else
   gencheck_cop1_unusable();
   mov_eax_memoffs32((unsigned int*)(&reg_cop1_double[dst->f.r.nrd]));
   mov_reg32_preg32(EBX, EAX);
   mov_reg32_preg32pimm32(ECX, EAX, 4);
   mov_m32_reg32((unsigned int*)dst->f.r.rt, EBX);
   mov_m32_reg32(((unsigned int*)dst->f.r.rt)+1, ECX);
#endif
}
Esempio n. 4
0
void genmfc1(void)
{
#ifdef INTERPRET_MFC1
   gencallinterp((unsigned int)MFC1, 0);
#else
   gencheck_cop1_unusable();
   mov_eax_memoffs32((unsigned int*)(&reg_cop1_simple[dst->f.r.nrd]));
   mov_reg32_preg32(EBX, EAX);
   mov_m32_reg32((unsigned int*)dst->f.r.rt, EBX);
   sar_reg32_imm8(EBX, 31);
   mov_m32_reg32(((unsigned int*)dst->f.r.rt)+1, EBX);
#endif
}
Esempio n. 5
0
void genmov_d(usf_state_t * state)
{
#ifdef INTERPRET_MOV_D
   gencallinterp(state, (unsigned int)state->current_instruction_table.MOV_D, 0);
#else
   gencheck_cop1_unusable(state);
   mov_eax_memoffs32(state, (unsigned int *)(&state->reg_cop1_double[state->dst->f.cf.fs]));
   mov_reg32_preg32(state, EBX, EAX);
   mov_reg32_preg32pimm32(state, ECX, EAX, 4);
   mov_eax_memoffs32(state, (unsigned int *)(&state->reg_cop1_double[state->dst->f.cf.fd]));
   mov_preg32_reg32(state, EAX, EBX);
   mov_preg32pimm32_reg32(state, EAX, 4, ECX);
#endif
}
Esempio n. 6
0
void genmov_d()
{
#ifdef INTERPRET_MOV_D
   gencallinterp((unsigned long)MOV_D, 0);
#else
   gencheck_cop1_unusable();
   mov_eax_memoffs32((unsigned long *)(&reg_cop1_double[dst->f.cf.fs]));
   mov_reg32_preg32(EBX, EAX);
   mov_reg32_preg32pimm32(ECX, EAX, 4);
   mov_eax_memoffs32((unsigned long *)(&reg_cop1_double[dst->f.cf.fd]));
   mov_preg32_reg32(EAX, EBX);
   mov_preg32pimm32_reg32(EAX, 4, ECX);
#endif
}
Esempio n. 7
0
void genmov_s(void)
{
#ifdef INTERPRET_MOV_S
   gencallinterp((native_type)cached_interpreter_table.MOV_S, 0);
#else
   gencheck_cop1_unusable();
#ifdef __x86_64__
   mov_xreg64_m64rel(RAX, (unsigned long long *)(&reg_cop1_simple[dst->f.cf.fs]));
   mov_reg32_preg64(EBX, RAX);
   mov_xreg64_m64rel(RAX, (unsigned long long *)(&reg_cop1_simple[dst->f.cf.fd]));
   mov_preg64_reg32(RAX, EBX);
#else
   mov_eax_memoffs32((unsigned int *)(&reg_cop1_simple[dst->f.cf.fs]));
   mov_reg32_preg32(EBX, EAX);
   mov_eax_memoffs32((unsigned int *)(&reg_cop1_simple[dst->f.cf.fd]));
   mov_preg32_reg32(EAX, EBX);
#endif
#endif
}
Esempio n. 8
0
void gendmfc1(void)
{
#ifdef INTERPRET_DMFC1
   gencallinterp((native_type)cached_interpreter_table.DMFC1, 0);
#else
   gencheck_cop1_unusable();
#ifdef __x86_64__
   mov_xreg64_m64rel(RAX, (unsigned long long *) (&reg_cop1_double[dst->f.r.nrd]));
   mov_reg32_preg64(EBX, RAX);
   mov_reg32_preg64pimm32(ECX, RAX, 4);
   mov_m32rel_xreg32((unsigned int*)dst->f.r.rt, EBX);
   mov_m32rel_xreg32(((unsigned int*)dst->f.r.rt)+1, ECX);
#else
   mov_eax_memoffs32((unsigned int*)(&reg_cop1_double[dst->f.r.nrd]));
   mov_reg32_preg32(EBX, EAX);
   mov_reg32_preg32pimm32(ECX, EAX, 4);
   mov_m32_reg32((unsigned int*)dst->f.r.rt, EBX);
   mov_m32_reg32(((unsigned int*)dst->f.r.rt)+1, ECX);
#endif
#endif
}