/* ************************************************************************ * * Setup the architecture * */ static void __init mpc834x_itx_setup_arch(void) { struct device_node *np; if (ppc_md.progress) ppc_md.progress("mpc834x_itx_setup_arch()", 0); np = of_find_node_by_type(NULL, "cpu"); if (np != 0) { const unsigned int *fp = get_property(np, "clock-frequency", NULL); if (fp != 0) loops_per_jiffy = *fp / HZ; else loops_per_jiffy = 50000000 / HZ; of_node_put(np); } #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") mpc83xx_add_bridge(np); ppc_md.pci_exclude_device = mpc83xx_exclude_device; #endif #ifdef CONFIG_ROOT_NFS ROOT_DEV = Root_NFS; #else ROOT_DEV = Root_HDA1; #endif }
/* ************************************************************************ * * Setup the architecture * */ static void __init mpc832x_rdb_setup_arch(void) { #if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE) struct device_node *np; #endif if (ppc_md.progress) ppc_md.progress("mpc832x_rdb_setup_arch()", 0); #ifdef CONFIG_PCI for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) mpc83xx_add_bridge(np); ppc_md.pci_exclude_device = mpc83xx_exclude_device; #endif #ifdef CONFIG_QUICC_ENGINE qe_reset(); if ((np = of_find_node_by_name(np, "par_io")) != NULL) { par_io_init(np); of_node_put(np); for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) par_io_of_config(np); } #endif /* CONFIG_QUICC_ENGINE */ }
static void __init mpc831x_rdb_setup_arch(void) { #ifdef CONFIG_PCI struct device_node *np; #endif if (ppc_md.progress) ppc_md.progress("mpc831x_rdb_setup_arch()", 0); #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") mpc83xx_add_bridge(np); for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie") mpc83xx_add_bridge(np); #endif mpc831x_usb_cfg(); }
/* ************************************************************************ * * Setup the architecture * */ static void __init sbc834x_setup_arch(void) { #ifdef CONFIG_PCI struct device_node *np; #endif if (ppc_md.progress) ppc_md.progress("sbc834x_setup_arch()", 0); #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") mpc83xx_add_bridge(np); #endif }
static void __init mpc5121_ads_setup_arch(void) { #ifdef CONFIG_PCI struct device_node *np; #endif printk(KERN_INFO "MPC5121 ADS board from Freescale Semiconductor\n"); /* * cpld regs are needed early */ mpc5121_ads_cpld_map(); #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,mpc5121-pci") mpc83xx_add_bridge(np); #endif }
/* ************************************************************************ * * Setup the architecture * */ static void __init mpc832x_sys_setup_arch(void) { struct device_node *np; u8 __iomem *bcsr_regs = NULL; if (ppc_md.progress) ppc_md.progress("mpc832x_sys_setup_arch()", 0); /* Map BCSR area */ np = of_find_node_by_name(NULL, "bcsr"); if (np) { struct resource res; of_address_to_resource(np, 0, &res); bcsr_regs = ioremap(res.start, res.end - res.start +1); of_node_put(np); } #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") mpc83xx_add_bridge(np); #endif #ifdef CONFIG_QUICC_ENGINE qe_reset(); if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) { par_io_init(np); of_node_put(np); for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) par_io_of_config(np); } if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) != NULL) { /* Reset the Ethernet PHYs */ #define BCSR8_FETH_RST 0x50 clrbits8(&bcsr_regs[8], BCSR8_FETH_RST); udelay(1000); setbits8(&bcsr_regs[8], BCSR8_FETH_RST); iounmap(bcsr_regs); of_node_put(np); } #endif /* CONFIG_QUICC_ENGINE */ }
/* ************************************************************************ * * Setup the architecture * */ static void __init mpc832x_sys_setup_arch(void) { struct device_node *np; if (ppc_md.progress) ppc_md.progress("mpc832x_sys_setup_arch()", 0); /* Map BCSR area */ np = of_find_node_by_name(NULL, "bcsr"); if (np != 0) { struct resource res; of_address_to_resource(np, 0, &res); bcsr_regs = ioremap(res.start, res.end - res.start +1); of_node_put(np); } #ifdef CONFIG_PCI for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) mpc83xx_add_bridge(np); ppc_md.pci_exclude_device = mpc83xx_exclude_device; #endif #ifdef CONFIG_QUICC_ENGINE qe_reset(); if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) { par_io_init(np); of_node_put(np); for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) par_io_of_config(np); } if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) != NULL){ /* Reset the Ethernet PHY */ bcsr_regs[9] &= ~0x20; udelay(1000); bcsr_regs[9] |= 0x20; iounmap(bcsr_regs); of_node_put(np); } #endif /* CONFIG_QUICC_ENGINE */ }
/* ************************************************************************ * * Setup the architecture * */ static void __init mpc836x_mds_setup_arch(void) { struct device_node *np; u8 __iomem *bcsr_regs = NULL; if (ppc_md.progress) ppc_md.progress("mpc836x_mds_setup_arch()", 0); /* Map BCSR area */ np = of_find_node_by_name(NULL, "bcsr"); if (np) { struct resource res; of_address_to_resource(np, 0, &res); bcsr_regs = ioremap(res.start, resource_size(&res)); of_node_put(np); } #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") mpc83xx_add_bridge(np); #endif #ifdef CONFIG_QUICC_ENGINE qe_reset(); if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) { par_io_init(np); of_node_put(np); for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) par_io_of_config(np); #ifdef CONFIG_QE_USB /* Must fixup Par IO before QE GPIO chips are registered. */ par_io_config_pin(1, 2, 1, 0, 3, 0); /* USBOE */ par_io_config_pin(1, 3, 1, 0, 3, 0); /* USBTP */ par_io_config_pin(1, 8, 1, 0, 1, 0); /* USBTN */ par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */ par_io_config_pin(1, 9, 2, 1, 3, 0); /* USBRP */ par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN */ par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21 */ #endif /* CONFIG_QE_USB */ } if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) != NULL){ uint svid; /* Reset the Ethernet PHY */ #define BCSR9_GETHRST 0x20 clrbits8(&bcsr_regs[9], BCSR9_GETHRST); udelay(1000); setbits8(&bcsr_regs[9], BCSR9_GETHRST); /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */ svid = mfspr(SPRN_SVR); if (svid == 0x80480021) { void __iomem *immap; immap = ioremap(get_immrbase() + 0x14a8, 8); /* * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) */ setbits32(immap, 0x0c003000); /* * IMMR + 0x14AC[20:27] = 10101010 * (data delay for both UCC's) */ clrsetbits_be32(immap + 4, 0xff0, 0xaa0); iounmap(immap); } iounmap(bcsr_regs); of_node_put(np); } #endif /* CONFIG_QUICC_ENGINE */ }
#include <linux/stddef.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/errno.h> #include <linux/reboot.h> #include <linux/pci.h> #include <linux/kdev_t.h> #include <linux/major.h> #include <linux/console.h> #include <linux/delay.h> #include <linux/seq_file.h> #include <linux/root_dev.h> #include <linux/initrd.h> #include <linux/of_platform.h> #include <linux/of_device.h> #include <asm/system.h> #include <asm/atomic.h> #include <asm/time.h> #include <asm/io.h> #include <asm/machdep.h> #include <asm/ipic.h> #include <asm/irq.h> #include <asm/prom.h> #include <asm/udbg.h> #include <sysdev/fsl_soc.h> #include <sysdev/fsl_pci.h> #include <asm/qe.h> #include <asm/qe_ic.h> #include "mpc83xx.h" #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ static void __init kmeter1_setup_arch(void) { struct device_node *np; if (ppc_md.progress) ppc_md.progress("kmeter1_setup_arch()", 0); #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") mpc83xx_add_bridge(np); #endif #ifdef CONFIG_QUICC_ENGINE qe_reset(); np = of_find_node_by_name(NULL, "par_io"); if (np != NULL) { par_io_init(np); of_node_put(np); for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) par_io_of_config(np); } np = of_find_compatible_node(NULL, "network", "ucc_geth"); if (np != NULL) { uint svid; /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */ svid = mfspr(SPRN_SVR); if (SVR_REV(svid) == 0x0021) { struct device_node *np_par; struct resource res; void __iomem *base; int ret; np_par = of_find_node_by_name(NULL, "par_io"); if (np_par == NULL) { printk(KERN_WARNING "%s couldn;t find par_io node\n", __func__); return; } /* Map Parallel I/O ports registers */ ret = of_address_to_resource(np_par, 0, &res); if (ret) { printk(KERN_WARNING "%s couldn;t map par_io registers\n", __func__); return; } base = ioremap(res.start, res.end - res.start + 1); /* * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) */ setbits32((base + 0xa8), 0x0c003000); /* * IMMR + 0x14AC[20:27] = 10101010 * (data delay for both UCC's) */ clrsetbits_be32((base + 0xac), 0xff0, 0xaa0); iounmap(base); of_node_put(np_par); } of_node_put(np); } #endif /* CONFIG_QUICC_ENGINE */ }
/* * Setup the architecture */ static void __init mpc8309_som_setup_arch(void) { void __iomem *immap; #ifdef CONFIG_PCI struct device_node *np; #endif if (ppc_md.progress) ppc_md.progress("mpc8309_som_setup_arch()", 0); #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") mpc83xx_add_bridge(np); #endif #ifdef CONFIG_USB_SUPPORT mpc8309_usb_cfg(); #endif immap = ioremap(get_immrbase(), 0x1000); /* set the I/O configuration for I2C2 */ clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC8309_SICRL_I2C2_MASK, MPC8309_SICRL_I2C2); #ifdef CONFIG_FLEXCAN_MPC830X /* Set I/O configuration for FlexCAN - CAN1 */ clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC8309_SICRL_CAN1_MASK, MPC8309_SICRL_CAN1); #if 1 clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC8309_SICRL_CAN2_MASK, MPC8309_SICRL_CAN2); clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC8309_SICRL_CAN3_MASK, MPC8309_SICRL_CAN3); clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC8309_SICRL_CAN4_MASK, MPC8309_SICRL_CAN4); #endif /* Set CAN access control register for normal supervisor mode */ clrsetbits_be32(immap + MPC830X_CAN_CTRL_OFFS, MPC830X_CAN1_CTRL_MASK, MPC830X_CAN1_SUPV_MODE); #if 1 clrsetbits_be32(immap + MPC830X_CAN_CTRL_OFFS, MPC830X_CAN2_CTRL_MASK, MPC830X_CAN2_SUPV_MODE); clrsetbits_be32(immap + MPC830X_CAN_CTRL_OFFS, MPC830X_CAN3_CTRL_MASK, MPC830X_CAN3_SUPV_MODE); clrsetbits_be32(immap + MPC830X_CAN_CTRL_OFFS, MPC830X_CAN4_CTRL_MASK, MPC830X_CAN4_SUPV_MODE); #endif #endif #ifdef CONFIG_QUICC_ENGINE #ifdef CONFIG_UCC_TDM_IO /* set the I/O configuration for TDM2 for SLIC */ clrsetbits_be32(immap + MPC83XX_SICRH_OFFS, MPC8309_SICRH_TDM2_MASK, MPC8309_SICRH_TDM2); /* set up BRG3 & BRG9 for SLIC */ clrsetbits_be32(immap + MPC83XX_SICRH_OFFS, 0x000c0000, 0x000c0000); #endif #ifdef CONFIG_UCC_TDM_FRAMER_IO /* set the I/O configuration for TDM1 for T1/E1 framer */ clrsetbits_be32(immap + MPC83XX_SICRH_OFFS, MPC8309_SICRH_TDM1_MASK, MPC8309_SICRH_TDM1); #endif qe_reset(); #endif /* CONFIG_QUICC_ENGINE */ iounmap(immap); }