/* number of CPUs */
int elg_pform_num_cpus() {
return mpconf(_MIPS_MP_NPROCESSORS);
}
void
mpinit(void)
{
struct mp *mp;
struct mpconf *conf;
struct mpcpu *cpu;
struct mpioapic *ioapic;
uint8_t *u8ptr;
uint8_t *lim;
// mpbootcpu = &mpcputab[0];
conf = mpconf(&mp);
if (!conf) {
return;
}
// cpuinit((struct m_cpu *)mpbootcpu);
mpmultiproc = 1;
mpapic = conf->apicadr;
for (u8ptr = (uint8_t *)(conf + 1), lim = (uint8_t *)conf + conf->len ;
u8ptr < lim ; ) {
switch (*u8ptr) {
case MPCPU:
cpu = (struct mpcpu *)u8ptr;
if (mpncpu != cpu->id) {
mpmultiproc = 0;
}
if (cpu->flags & MPCPUBOOT) {
mpbootcpu = &mpcputab[mpncpu];
cpuinit((struct m_cpu *)mpbootcpu);
}
mpcputab[mpncpu].id = mpncpu;
mpncpu++;
u8ptr += sizeof(struct mpcpu);
continue;
case MPIOAPIC:
ioapic = (struct mpioapic *)u8ptr;
mpioapicid = ioapic->apicnum;
mpioapic = ioapic->adr;
u8ptr += sizeof(struct mpioapic);
continue;
case MPBUS:
case MPIOINTR:
case MPLINTR:
u8ptr += 8;
continue;
default:
mpmultiproc = 0;
break;
}
}
if ((mpncpu == 1) || !mpmultiproc) {
mpncpu = 1;
// mptab = NULL;
// mpioapicid = 0;
return;
} else if (mp->intmode) {
outb(0x70, 0x22); // select IMCR
outb(inb(0x23) | 0x01, 0x23); // mask external timer interrupts
}
#if 0
/* Boot CPU */
/* local APIC initialisation where present */
// apicinit(0);
/* I/O APIC initialisation */
// ioapicinit(0);
#endif
return;
}
void
mpinit(void)
{
struct mp *mp;
struct mpconf *conf;
struct mpcpu *cpu;
struct mpioapic *ioapic;
long unit;
uint8_t *u8ptr;
uint8_t *lim;
conf = mpconf(&mp);
if (!conf) {
return;
}
mpapic = conf->apicadr;
for (u8ptr = (uint8_t *)(conf + 1), lim = (uint8_t *)conf + conf->len ;
u8ptr < lim ; ) {
switch (*u8ptr) {
case MPCPU:
cpu = (struct mpcpu *)u8ptr;
unit = cpu->id;
if (cpu->flags & MPCPUBOOT) {
mpbootcpu = &cputab[unit];
taskinittls(unit, PROCKERN);
}
cputab[unit].unit = unit;
mpncpu++;
u8ptr += sizeof(struct mpcpu);
continue;
case MPIOAPIC:
ioapic = (struct mpioapic *)u8ptr;
mpioapicid = ioapic->apicnum;
mpioapic = ioapic->adr;
u8ptr += sizeof(struct mpioapic);
continue;
case MPBUS:
case MPIOINTR:
case MPLINTR:
u8ptr += 8;
continue;
default:
mpmultiproc = 0;
break;
}
}
if (mpncpu > 1) {
mpmultiproc = 1;
} else {
return;
}
if (mp->intmode) {
outb(0x70, 0x22); // select IMCR
outb(inb(0x23) | 0x01, 0x23); // mask external timer interrupts
}
#if 0
/* Boot CPU */
/* local APIC initialisation where present */
// apicinit();
/* I/O APIC initialisation */
// ioapicinit();
#endif
return;
}
