static void save_memory_training_data(bool s3wake, uint32_t fsp_version) { size_t mrc_data_size; const void *mrc_data; if (!CONFIG(CACHE_MRC_SETTINGS) || s3wake) return; mrc_data = fsp_find_nv_storage_data(&mrc_data_size); if (!mrc_data) { printk(BIOS_ERR, "Couldn't find memory training data HOB.\n"); return; } /* * Save MRC Data to CBMEM. By always saving the data this forces * a retrain after a trip through Chrome OS recovery path. The * code which saves the data to flash doesn't write if the latest * training data matches this one. */ if (mrc_cache_stash_data(MRC_TRAINING_DATA, fsp_version, mrc_data, mrc_data_size) < 0) printk(BIOS_ERR, "Failed to stash MRC data\n"); if (CONFIG(FSP2_0_USES_TPM_MRC_HASH)) mrc_cache_update_hash(mrc_data, mrc_data_size); }
void raminit(struct mrc_params *mp, int prev_sleep_state) { int ret; mrc_wrapper_entry_t mrc_entry; const struct mrc_saved_data *cache; /* Fill in default entries. */ mp->version = MRC_PARAMS_VER; mp->console_out = &send_to_console; mp->prev_sleep_state = prev_sleep_state; if (!mrc_cache_get_current(&cache)) { mp->saved_data_size = cache->size; mp->saved_data = &cache->data[0]; } else { printk(BIOS_DEBUG, "No MRC cache found.\n"); } mrc_entry = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab, NULL); if (mrc_entry == NULL) { printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); return; } if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS) enable_smbus(); ret = mrc_entry(mp); cbmem_initialize_empty(); printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret); printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", mp->data_to_save, mp->data_to_save_size); if (mp->data_to_save != NULL && mp->data_to_save_size > 0) mrc_cache_stash_data(mp->data_to_save, mp->data_to_save_size); }
void raminit(struct mrc_params *mp, int prev_sleep_state) { int ret; mrc_wrapper_entry_t mrc_entry; const struct mrc_saved_data *cache; /* Fill in default entries. */ mp->version = MRC_PARAMS_VER; mp->console_out = &send_to_console; mp->prev_sleep_state = prev_sleep_state; mp->rmt_enabled = IS_ENABLED(CONFIG_MRC_RMT); /* Default to 2GiB IO hole. */ if (!mp->io_hole_mb) mp->io_hole_mb = 2048; if (vboot_recovery_mode_enabled()) { printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); } else if (!mrc_cache_get_current(&cache)) { mp->saved_data_size = cache->size; mp->saved_data = &cache->data[0]; } else if (prev_sleep_state == ACPI_S3) { /* If waking from S3 and no cache then. */ printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); post_code(POST_RESUME_FAILURE); reset_system(); } else { printk(BIOS_DEBUG, "No MRC cache found.\n"); #if CONFIG_EC_GOOGLE_CHROMEEC if (prev_sleep_state == ACPI_S0) { /* Ensure EC is running RO firmware. */ google_chromeec_check_ec_image(EC_IMAGE_RO); } #endif } /* Determine if mrc.bin is in the cbfs. */ if (cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL) == NULL) { printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); return; } /* * The entry point is currently the first instruction. Handle the * case of an ELF file being put in the cbfs by setting the entry * to the CONFIG_MRC_BIN_ADDRESS. */ mrc_entry = (void *)(uintptr_t)CONFIG_MRC_BIN_ADDRESS; if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS) enable_smbus(); ret = mrc_entry(mp); print_dram_info(); if (prev_sleep_state != ACPI_S3) { cbmem_initialize_empty(); } else if (cbmem_initialize()) { #if CONFIG_HAVE_ACPI_RESUME printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ reset_system(); #endif } printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret); printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", mp->data_to_save, mp->data_to_save_size); if (mp->data_to_save != NULL && mp->data_to_save_size > 0) mrc_cache_stash_data(mp->data_to_save, mp->data_to_save_size); }
asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; uintptr_t top_of_ram; bool s3wake; struct chipset_power_state *ps = pmc_get_power_state(); void *smm_base; size_t smm_size, var_size; const void *new_var_data; uintptr_t tseg_base; timestamp_add_now(TS_START_ROMSTAGE); soc_early_romstage_init(); console_init(); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); if (punit_init()) set_max_freq(); else printk(BIOS_DEBUG, "Punit failed to initialize properly\n"); /* Stash variable MRC data and let cache system update it later */ new_var_data = fsp_find_extension_hob_by_guid(hob_variable_guid, &var_size); if (new_var_data) mrc_cache_stash_data(MRC_VARIABLE_DATA, car_get_var(fsp_version), new_var_data, var_size); else printk(BIOS_ERR, "Failed to determine variable data\n"); if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); mainboard_save_dimm_info(); /* * We need to make sure ramstage will be run cached. At this point exact * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ top_of_ram = (uintptr_t) cbmem_top(); /* cbmem_top() needs to be at least 16 MiB aligned */ assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); /* * Cache the TSEG region at the top of ram. This region is * not restricted to SMM mode until SMM has been relocated. * By setting the region to cacheable it provides faster access * when relocating the SMM handler as well as using the TSEG * region for other purposes. */ smm_region_info(&smm_base, &smm_size); tseg_base = (uintptr_t)smm_base; postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); run_postcar_phase(&pcf); }
asmlinkage void car_stage_entry(void) { void *hob_list_ptr; const void *mrc_data; struct range_entry fsp_mem, reg_car; struct postcar_frame pcf; size_t mrc_data_size; uintptr_t top_of_ram; int prev_sleep_state; struct romstage_handoff *handoff; struct chipset_power_state *ps = car_get_var_ptr(&power_state); timestamp_add_now(TS_START_ROMSTAGE); soc_early_romstage_init(); disable_watchdog(); console_init(); prev_sleep_state = fill_power_state(ps); /* Make sure the blob does not override our data in CAR */ range_entry_init(®_car, (uintptr_t)_car_relocatable_data_end, (uintptr_t)_car_region_end, 0); if (fsp_memory_init(&hob_list_ptr, ®_car) != FSP_SUCCESS) { die("FSP memory init failed. Giving up."); } fsp_find_reserved_memory(&fsp_mem, hob_list_ptr); /* initialize cbmem by adding FSP reserved memory first thing */ if (prev_sleep_state != SLEEP_STATE_S3) { cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, range_entry_size(&fsp_mem)); } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, range_entry_size(&fsp_mem))) { if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ hard_reset(); } } /* make sure FSP memory is reserved in cbmem */ if (range_entry_base(&fsp_mem) != (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) die("Failed to accommodate FSP reserved memory request"); /* Now that CBMEM is up, save the list so ramstage can use it */ fsp_save_hob_list(hob_list_ptr); /* Save MRC Data to CBMEM */ if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) && (prev_sleep_state != SLEEP_STATE_S3)) { mrc_data = fsp_find_nv_storage_data(&mrc_data_size); if (mrc_data && mrc_cache_stash_data(mrc_data, mrc_data_size) < 0) printk(BIOS_ERR, "Failed to stash MRC data\n"); } /* Create romstage handof information */ handoff = romstage_handoff_find_or_add(); if (handoff != NULL) handoff->s3_resume = (prev_sleep_state == SLEEP_STATE_S3); else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); /* * We need to make sure ramstage will be run cached. At this point exact * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ top_of_ram = (uintptr_t) cbmem_top(); /* cbmem_top() needs to be at least 16 MiB aligned */ assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); run_postcar_phase(&pcf); }