void __init msm9615_init_irq(void) { struct msm_mpm_device_data *data = NULL; #ifdef CONFIG_MSM_MPM data = &msm9615_mpm_dev_data; #endif msm_mpm_irq_extn_init(data); gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, (void *)MSM_QGIC_CPU_BASE); }
void __init msm9615_init_irq(void) { msm_mpm_irq_extn_init(); gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, (void *)MSM_QGIC_CPU_BASE); /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ writel_relaxed(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); writel_relaxed(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); mb(); }
void __init msm9615_init_irq(void) { unsigned int i; msm_mpm_irq_extn_init(); gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, (void *)MSM_QGIC_CPU_BASE); /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ writel_relaxed(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); writel_relaxed(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); mb(); /* * FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet * as they are configured as level, which does not play nice with * handle_percpu_irq. */ for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) irq_set_handler(i, handle_percpu_irq); } }
void __init msm9615_init_irq(void) { msm_mpm_irq_extn_init(); gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, (void *)MSM_QGIC_CPU_BASE); }