void dummy_ap_irq_handler(unsigned int irq)
{
switch(irq){
case MT_MD_WDT1_IRQ_ID:
md_wdt_irq_handler(MT_MD_WDT1_IRQ_ID);
mt_irq_ack(MT_MD_WDT1_IRQ_ID);
mt_irq_unmask(MT_MD_WDT1_IRQ_ID);
break;
default:
break;
}
}
status_t platform_set_periodic_timer(platform_timer_callback callback, void *arg, time_t interval)
{
time_callback = callback;
tick_interval = interval;
callback_arg = arg;
DRV_WriteReg32(GPT_IRQEN_REG, 0);
DRV_WriteReg32(GPT_IRQACK_REG, 0x3f);
mt_irq_set_sens(MT6575_GPT_IRQ_ID, MT65xx_LEVEL_SENSITIVE);
mt_irq_set_polarity(MT6575_GPT_IRQ_ID, MT65xx_POLARITY_LOW);
DRV_WriteReg32(GPT5_CON_REG, 0x02);
DRV_WriteReg32(GPT_IRQACK_REG, 0x10);
DRV_WriteReg32(GPT5_COMPARE_REG, TIMER_TICK_RATE*interval/1000);
DRV_WriteReg32(GPT_IRQEN_REG, 0x10);
mt_irq_unmask(MT6575_GPT_IRQ_ID);
DRV_WriteReg32(GPT5_CON_REG, GPT_ENABLE|GPT_MODE4_ONE_SHOT);
return NO_ERROR;
}
void APDMA_test_transfer(int testcase)
{
int i, channel;
int start_dma;
unsigned int cnt = 20;
channel = mt_req_gdma(GDMA_ANY);
printk("GDMA channel:%d\n",channel);
if(channel < 0 ){
printk("ERROR Register DMA\n");
return;
}
mt_reset_gdma_conf(channel);
dma_dst_array_v = dma_alloc_coherent(NULL, TEST_LEN, &dma_dst_array_p, GFP_KERNEL ); // 25 unsinged int
dma_src_array_v = dma_alloc_coherent(NULL, TEST_LEN, &dma_src_array_p, GFP_KERNEL );
struct mt_gdma_conf dma_conf = {
.count = TEST_LEN,
.src = dma_src_array_p,
.dst = dma_dst_array_p,
.iten = (testcase == 2) ? DMA_FALSE : DMA_TRUE,
.isr_cb = (testcase == 2) ? NULL : irq_dma_handler,
.data = channel,
.burst = DMA_CON_BURST_SINGLE,
.dfix = DMA_FALSE,
.sfix = DMA_FALSE,
//.cohen = DMA_TRUE, //enable coherence bus
.sec = DMA_FALSE, // non-security channel
.domain = 0,
.limiter = (testcase == 3 || testcase == 4) ? 0x3FF : 0,
};
for(i = 0; i < LEN; i++) {
dma_dst_array_v[i] = 0;
dma_src_array_v[i] = i;
}
if ( mt_config_gdma(channel, &dma_conf, ALL) != 0) {
printk("ERROR set DMA\n");
goto _exit;
return;
}
/*
unsigned int dma_src = readl(DMA_SRC(DMA_BASE_CH(channel)));
unsigned int dma_dst = readl(DMA_DST);
unsigned int len = readl(DMA_LEN1);
printk("start dma channel %d src = 0x%x, dst = 0x%x, len = %d bytes\n", channel, dma_src, dma_dst, len);
*/
start_dma=mt_start_gdma(channel);
#ifdef CONFIG_OF
mt_irq_dump_status(cqdma_irq_num);
#else
mt_irq_dump_status(CQ_DMA_IRQ_BIT_ID);
#endif
printk("Start %d\n",start_dma);
switch(testcase)
{
case 1:
while(!DMA_INT_DONE);
#ifdef CONFIG_OF
mt_irq_dump_status(cqdma_irq_num);
#else
mt_irq_dump_status(CQ_DMA_IRQ_BIT_ID);
#endif
DMA_INT_DONE=0;
break;
case 2:
if (mt_polling_gdma(channel, GDMA_WARM_RST_TIMEOUT) != 0)
printk("Polling transfer failed\n");
else
printk("Polling succeeded\n");
mt_free_gdma(channel);
break;
case 3:
mt_warm_reset_gdma(channel);
for(i = 0; i < LEN; i++) {
if(dma_dst_array_v[i] != dma_src_array_v[i]) {
printk("Warm reset succeeded\n");
break;
}
mt_free_gdma(channel);
}
if(i == LEN)
printk("Warm reset failed\n");
break;
case 4:
mt_hard_reset_gdma(channel);
for(i = 0; i < LEN; i++) {
if(dma_dst_array_v[i] != dma_src_array_v[i]) {
printk("Hard reset succeeded\n");
break;
}
mt_free_gdma(channel);
}
if(i == LEN)
printk("Hard reset failed\n");
break;
case 5:
do {
mdelay(50);
printk("GIC mask test cnt = %d\n", cnt);
if (cnt-- == 0) {
mt_irq_unmask(irq_get_irq_data(cqdma_irq_num));
printk("GIC Mask PASS !!!\n");
break;
}
}while(!DMA_INT_DONE);
#ifdef CONFIG_OF
mt_irq_dump_status(cqdma_irq_num);
#else
mt_irq_dump_status(CQ_DMA_IRQ_BIT_ID);
#endif
DMA_INT_DONE=0;
break;
case 6:
do {
mdelay(50);
printk("GIC ack test cnt = %d\n", cnt);
if (cnt-- == 0) {
mt_irq_mask_restore(&mask);
printk("GIC Mask All PASS !!!\n");
break;
}
}while(!DMA_INT_DONE);
#ifdef CONFIG_OF
mt_irq_dump_status(cqdma_irq_num);
#else
mt_irq_dump_status(CQ_DMA_IRQ_BIT_ID);
#endif
DMA_INT_DONE=0;
break;
default:
break;
}
_exit:
if(dma_dst_array_v){
dma_free_coherent(NULL, TEST_LEN, dma_dst_array_v, dma_dst_array_p);
dma_dst_array_v = dma_dst_array_p = NULL;
}
if(dma_src_array_v){
dma_free_coherent(NULL, TEST_LEN, dma_src_array_v, dma_src_array_p);
dma_src_array_v = dma_src_array_p = NULL;
}
return;
}
static ssize_t cqdma_dvt_show(struct device_driver *driver, char *buf)
{
return snprintf(buf, PAGE_SIZE, "==CQDMA test==\n"
"1.CQDMA transfer (interrupt mode)\n"
"2.CQDMA transfer (polling mode)\n"
"3.CQDMA warm reset\n"
"4.CQDMA hard reset\n"
"5.Mask CQDMA interrupt test\n"
"6.Mask all CQDMA interrupt test\n"
);
}
static ssize_t cqdma_dvt_store(struct device_driver *driver, const char *buf, size_t count)
{
char *p = (char *)buf;
unsigned int num;
num = simple_strtoul(p, &p, 10);
switch(num){
/* Test APDMA Normal Function */
case 1:
APDMA_test_transfer(1);
break;
case 2:
APDMA_test_transfer(2);
break;
case 3:
APDMA_test_transfer(3);
break;
case 4:
APDMA_test_transfer(4);
break;
case 5:
mt_irq_mask(irq_get_irq_data(cqdma_irq_num));
APDMA_test_transfer(5);
break;
case 6:
mt_irq_mask_all(&mask);
APDMA_test_transfer(6);
break;
default:
break;
}
return count;
}
void md_wdt_init(void)
{
mt_irq_set_sens(MT_MD_WDT1_IRQ_ID, MT65xx_EDGE_SENSITIVE);
mt_irq_set_polarity(MT_MD_WDT1_IRQ_ID, MT65xx_POLARITY_LOW);
mt_irq_unmask(MT_MD_WDT1_IRQ_ID);
}