/*---------------------------------------------------------------------------+ * program_ecc. *---------------------------------------------------------------------------*/ static void program_ecc(unsigned long start_address, unsigned long num_bytes) { u32 val; char str[] = "ECC generation -"; #if defined(CONFIG_PRAM) u32 *magicPtr; u32 magic; if ((mfspr(dbcr0) & 0x80000000) == 0) { /* only if no external debugger is alive! * Check whether vxWorks is using EDR logging, if yes zero * also PostMortem and user reserved memory */ magicPtr = (u32 *)(start_address + num_bytes - (CONFIG_PRAM*1024) + sizeof(u32)); magic = in_be32(magicPtr); debug("%s: CONFIG_PRAM %d kB magic 0x%x 0x%p\n", __FUNCTION__, CONFIG_PRAM, magicPtr, magic); if (magic == 0xbeefbabe) { printf("%s: preserving at %p\n", __FUNCTION__, magicPtr); num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM; } } #endif sync(); eieio(); puts(str); /* ECC bit set method for cached memory */ /* Fast method, no noticeable delay */ dcbz_area(start_address, num_bytes); dflush(); blank_string(strlen(str)); /* Clear error status */ mfsdram(DDR0_00, val); mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); /* * Clear possible ECC errors * If not done, then we could get an interrupt later on when * exceptions are enabled. */ mtspr(mcsr, mfspr(mcsr)); /* Set 'int_mask' parameter to functionnal value */ mfsdram(DDR0_01, val); mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF)); return; }
static void program_ecc(u32 start_address, u32 num_bytes, u32 tlb_word2_i_value) { u32 val; u32 current_addr = start_address; u32 size; int bytes_remaining; sync(); wait_ddr_idle(); /* * Because of 440EPx errata CHIP 11, we don't touch the last 256 * bytes of SDRAM. */ bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE; /* * We have to write the ECC bytes by zeroing and flushing in smaller * steps, since the whole 256MByte takes too long for the external * watchdog. */ while (bytes_remaining > 0) { size = min((64 << 20), bytes_remaining); /* Write zero's to SDRAM */ dcbz_area(current_addr, size); /* Write modified dcache lines back to memory */ clean_dcache_range(current_addr, current_addr + size); current_addr += 64 << 20; bytes_remaining -= 64 << 20; WATCHDOG_RESET(); } sync(); wait_ddr_idle(); /* Clear error status */ mfsdram(DDR0_00, val); mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); /* Set 'int_mask' parameter to functionnal value */ mfsdram(DDR0_01, val); mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF)); sync(); wait_ddr_idle(); }
static void program_ddr0_43(unsigned long dimm_ranks[], unsigned char const iic0_dimm_addr[], unsigned long num_dimm_banks, unsigned long sdram_freq, unsigned long cols, unsigned long banks) { unsigned long dimm_num; unsigned long t_wr_ps = 0; unsigned long t_wr_clk; u32 ddr0_43 = DDR0_43_APREBIT_ENCODE(10) | DDR0_43_COLUMN_SIZE_ENCODE(12 - cols) | DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0); /*------------------------------------------------------------------ * Handle the timing. We need to find the worst case timing of all * the dimm modules installed. *-----------------------------------------------------------------*/ /* loop through all the DIMM slots on the board */ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_ranks[dimm_num]) { unsigned long ps; ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 36); t_wr_ps = max(t_wr_ps, ps); } } debug("t_wr_ps = %d\n", t_wr_ps); t_wr_clk = (MULDIV64(sdram_freq, t_wr_ps, ONE_BILLION) + 999) / 1000; mtsdram(DDR0_43, ddr0_43 | DDR0_43_TWR_ENCODE(t_wr_clk)); }
static void program_ddr0_44(unsigned long dimm_ranks[], unsigned char const iic0_dimm_addr[], unsigned long num_dimm_banks, unsigned long sdram_freq) { unsigned long dimm_num; unsigned long t_rcd_ps = 0; unsigned long t_rcd_clk; /*------------------------------------------------------------------ * Handle the timing. We need to find the worst case timing of all * the dimm modules installed. *-----------------------------------------------------------------*/ /* loop through all the DIMM slots on the board */ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_ranks[dimm_num]) { unsigned long ps; ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 29); t_rcd_ps = max(t_rcd_ps, ps); } } debug("t_rcd_ps = %d\n", t_rcd_ps); t_rcd_clk = (MULDIV64(sdram_freq, t_rcd_ps, ONE_BILLION) + 999) / 1000; mtsdram(DDR0_44, DDR0_44_TRCD_ENCODE(t_rcd_clk)); }
static void program_ddr0_06(unsigned long dimm_ranks[], unsigned char const iic0_dimm_addr[], unsigned long num_dimm_banks, unsigned long sdram_freq) { unsigned long dimm_num; unsigned char spd_40; unsigned long t_wtr_ps = 0; unsigned long t_rfc_ps = 0; unsigned long t_wtr_clk; unsigned long t_rfc_clk; u32 ddr0_06 = DDR0_06_WRITEINTERP_ENCODE(0x1) | DDR0_06_TDLL_ENCODE(200); /*------------------------------------------------------------------ * Handle the timing. We need to find the worst case timing of all * the dimm modules installed. *-----------------------------------------------------------------*/ /* loop through all the DIMM slots on the board */ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_ranks[dimm_num]) { unsigned long ps; /* tWTR */ ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 37); t_wtr_ps = max(t_wtr_ps, ps); /* tRFC */ ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 42); spd_40 = spd_read(iic0_dimm_addr[dimm_num], 40); ps += 256000 * (spd_40 & 0x01); switch ((spd_40 & 0x0E) >> 1) { case 0x1: ps += 250; break; case 0x2: ps += 333; break; case 0x3: ps += 500; break; case 0x4: ps += 667; break; case 0x5: ps += 750; break; } t_rfc_ps = max(t_rfc_ps, ps); } } debug("t_wtr_ps = %d\n", t_wtr_ps); t_wtr_clk = (MULDIV64(sdram_freq, t_wtr_ps, ONE_BILLION) + 999) / 1000; debug("t_rfc_ps = %d\n", t_rfc_ps); t_rfc_clk = (MULDIV64(sdram_freq, t_rfc_ps, ONE_BILLION) + 999) / 1000; mtsdram(DDR0_06, ddr0_06 | DDR0_06_TWTR_ENCODE(t_wtr_clk) | DDR0_06_TRFC_ENCODE(t_rfc_clk)); }
/* * void ecc_init() * * Description: * This routine initializes a range of DRAM ECC memory with known * data and enables ECC checking. * * TO DO: * - Improve performance by utilizing cache. * - Further generalize to make usable by other 4xx variants (e.g. * 440EPx, et al). * * Input(s): * start - A pointer to the start of memory covered by ECC requiring * initialization. * size - The size, in bytes, of the memory covered by ECC requiring * initialization. * * Output(s): * start - A pointer to the start of memory covered by ECC with * CFG_ECC_PATTERN written to all locations and ECC data * primed. * * Returns: * N/A */ void ecc_init(unsigned long * const start, unsigned long size) { const unsigned long pattern = CFG_ECC_PATTERN; unsigned long * const end = (unsigned long * const)((long)start + size); unsigned long * current = start; unsigned long mcopt1; long increment; if (start >= end) return; mfsdram(SDRAM_ECC_CFG, mcopt1); /* Enable ECC generation without checking or reporting */ mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) | SDRAM_ECC_CFG_MCHK_GEN)); increment = sizeof(u32); #if defined(CONFIG_440) /* * Look at the geometry of SDRAM (data width) to determine whether we * can skip words when writing. */ if ((mcopt1 & SDRAM_ECC_CFG_DMWD_MASK) != SDRAM_ECC_CFG_DMWD_32) increment = sizeof(u64); #endif /* defined(CONFIG_440) */ while (current < end) { *current = pattern; current = (unsigned long *)((long)current + increment); } /* Wait until the writes are finished. */ sync(); /* Enable ECC generation with checking and no reporting */ mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) | SDRAM_ECC_CFG_MCHK_CHK)); }
static void program_ddr0_11(unsigned long sdram_freq) { unsigned long const t_xsnr_ps = 200000; /* 200 ns */ unsigned long t_xsnr_clk; debug("t_xsnr_ps = %d\n", t_xsnr_ps); t_xsnr_clk = (MULDIV64(sdram_freq, t_xsnr_ps, ONE_BILLION) + 999) / 1000; mtsdram(DDR0_11, DDR0_11_SREFRESH_ENCODE(0) | DDR0_11_TXSNR_ENCODE(t_xsnr_clk) | DDR0_11_TXSR_ENCODE(200)); }
static void program_ddr0_27(unsigned long sdram_freq) { unsigned long const t_init_ps = 200000000; /* 200 us. init */ unsigned long t_init_clk; debug("t_init_ps = %d\n", t_init_ps); t_init_clk = (MULDIV64(sdram_freq, t_init_ps, ONE_BILLION) + 999) / 1000; mtsdram(DDR0_27, DDR0_27_EMRS_DATA_ENCODE(0x0000) | DDR0_27_TINIT_ENCODE(t_init_clk)); }
static void ecc_init(ulong start, ulong size) { ulong current_addr; /* current byte address */ ulong end_addr; /* end of memory region */ ulong addr_inc; /* address skip between writes */ ulong cfg0_reg; /* for restoring ECC state */ /* * TODO: Enable dcache before running this test (speedup) */ mfsdram(mem_cfg0, cfg0_reg); mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_GEN); /* * look at geometry of SDRAM (data width) to determine whether we * can skip words when writing */ if ((cfg0_reg & SDRAM_CFG0_DRAMWDTH) == SDRAM_CFG0_DRAMWDTH_32) addr_inc = 4; else addr_inc = 8; current_addr = start; end_addr = start + size; while (current_addr < end_addr) { *((ulong *)current_addr) = 0x00000000; current_addr += addr_inc; } /* * TODO: Flush dcache and disable it again */ /* * Enable ecc checking and parity errors */ mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_CHK); }
static void program_ddr0_10(unsigned long dimm_ranks[], unsigned long ranks) { unsigned long csmap; if (2 == ranks) { /* Both chip selects in use */ csmap = 0x03; } else { /* One chip select in use */ csmap = (1 == dimm_ranks[0]) ? 0x1 : 0x2; } mtsdram(DDR0_10, DDR0_10_WRITE_MODEREG_ENCODE(0x0) | DDR0_10_CS_MAP_ENCODE(csmap) | DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(0)); }
static void program_ddr0_22(unsigned long dimm_ranks[], unsigned char const iic0_dimm_addr[], unsigned long num_dimm_banks, unsigned long width) { #if defined(CONFIG_DDR_ECC) unsigned long dimm_num; unsigned long ecc_available = width >= 64; u32 ddr0_22 = DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) | DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) | DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS); /* loop through all the DIMM slots on the board */ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_ranks[dimm_num]) { /* Check for ECC */ if (0 == (spd_read(iic0_dimm_addr[dimm_num], 11) & 0x02)) { ecc_available = FALSE; } } } if (ecc_available) { debug("ECC found on all DIMMs present\n"); mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x3)); } else { debug("ECC not found on some or all DIMMs present\n"); mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x0)); } #else mtsdram(DDR0_22, DDR0_22_CTRL_RAW_ENCODE(0x0) | DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) | DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) | DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS)); #endif /* defined(CONFIG_DDR_ECC) */ }
static void program_ddr0_26(unsigned long sdram_freq) { unsigned long const t_ref_ps = 7800000; /* 7.8 us. refresh */ /* TODO: check definition of tRAS_MAX */ unsigned long const t_ras_max_ps = 9 * t_ref_ps; unsigned long t_ras_max_clk; unsigned long t_ref_clk; /* Round down t_ras_max_clk and t_ref_clk */ debug("t_ras_max_ps = %d\n", t_ras_max_ps); t_ras_max_clk = MULDIV64(sdram_freq, t_ras_max_ps, ONE_BILLION) / 1000; debug("t_ref_ps = %d\n", t_ref_ps); t_ref_clk = MULDIV64(sdram_freq, t_ref_ps, ONE_BILLION) / 1000; mtsdram(DDR0_26, DDR0_26_TRAS_MAX_ENCODE(t_ras_max_clk) | DDR0_26_TREF_ENCODE(t_ref_clk)); }
static void program_ddr0_24(unsigned long ranks) { u32 ddr0_24 = DDR0_24_RTT_PAD_TERMINATION_ENCODE(0x1) | /* 75 ohm */ DDR0_24_ODT_RD_MAP_CS1_ENCODE(0x0); if (2 == ranks) { /* Both chip selects in use */ ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x1) | DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x2); } else { /* One chip select in use */ /* One of the two fields added to ddr0_24 is a "don't care" */ ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x2) | DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x1); } mtsdram(DDR0_24, ddr0_24); }
long int init_sdram_static_settings(void) { /* disable memcontroller so updates work */ mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL); mtsdram(SDRAM0_RTR, MEM_RTR_INIT_VAL); mtsdram(SDRAM0_PMIT, MEM_PMIT_INIT_VAL); mtsdram(SDRAM0_B0CR, MEM_MB0CF_INIT_VAL); mtsdram(SDRAM0_B1CR, MEM_MB1CF_INIT_VAL); mtsdram(SDRAM0_TR, MEM_SDTR1_INIT_VAL); /* SDRAM have a power on delay, 500 micro should do */ udelay(500); mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE); return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */ }
static void program_ddr0_05(unsigned long dimm_ranks[], unsigned char const iic0_dimm_addr[], unsigned long num_dimm_banks, unsigned long sdram_freq) { unsigned long dimm_num; unsigned long t_rp_ps = 0; unsigned long t_ras_ps = 0; unsigned long t_rp_clk; unsigned long t_ras_clk; u32 ddr0_05 = DDR0_05_TMRD_ENCODE(0x2) | DDR0_05_TEMRS_ENCODE(0x2); /*------------------------------------------------------------------ * Handle the timing. We need to find the worst case timing of all * the dimm modules installed. *-----------------------------------------------------------------*/ /* loop through all the DIMM slots on the board */ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_ranks[dimm_num]) { unsigned long ps; /* tRP */ ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 27); t_rp_ps = max(t_rp_ps, ps); /* tRAS */ ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 30); t_ras_ps = max(t_ras_ps, ps); } } debug("t_rp_ps = %d\n", t_rp_ps); t_rp_clk = (MULDIV64(sdram_freq, t_rp_ps, ONE_BILLION) + 999) / 1000; debug("t_ras_ps = %d\n", t_ras_ps); t_ras_clk = (MULDIV64(sdram_freq, t_ras_ps, ONE_BILLION) + 999) / 1000; mtsdram(DDR0_05, ddr0_05 | DDR0_05_TRP_ENCODE(t_rp_clk) | DDR0_05_TRAS_MIN_ENCODE(t_ras_clk)); }
/* * Autodetect onboard DDR SDRAM on 440 platforms * * NOTE: Some of the hardcoded values are hardware dependant, * so this should be extended for other future boards * using this routine! */ phys_size_t initdram(int board_type) { int i; int tr1_bank1; #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ defined(CONFIG_440GR) || defined(CONFIG_440SP) /* * Soft-reset SDRAM controller. */ mtsdr(SDR0_SRST, SDR0_SRST_DMC); mtsdr(SDR0_SRST, 0x00000000); #endif for (i=0; i<N_MB0CF; i++) { /* * Disable memory controller. */ mtsdram(SDRAM0_CFG0, 0x00000000); /* * Setup some default */ mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ mtsdram(SDRAM0_WDDCTR, CONFIG_SYS_SDRAM0_WDDCTR); mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ mtsdram(SDRAM0_B0CR, mb0cf[i].reg); mtsdram(SDRAM0_TR0, CONFIG_SYS_SDRAM0_TR0); mtsdram(SDRAM0_TR1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/ mtsdram(SDRAM0_RTR, CONFIG_SYS_SDRAM0_RTR); mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/ udelay(400); /* Delay 200 usecs (min) */ /* * Enable the controller, then wait for DCEN to complete */ mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0); udelay(10000); if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) { phys_size_t size = mb0cf[i].size; /* * Optimize TR1 to current hardware environment */ sdram_tr1_set(0x00000000, &tr1_bank1); mtsdram(SDRAM0_TR1, (tr1_bank1 | 0x80800800)); /* * OK, size detected. Enable second bank if * defined (assumes same type as bank 0) */ #ifdef CONFIG_SDRAM_BANK1 mtsdram(SDRAM0_CFG0, 0); mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg); mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0); udelay(10000); /* * Check if 2nd bank is really available. * If the size not equal to the size of the first * bank, then disable the 2nd bank completely. */ if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) != mb0cf[i].size) { mtsdram(SDRAM0_CFG0, 0); mtsdram(SDRAM0_B1CR, 0); mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0); udelay(10000); } else { /* * We have two identical banks, so the size * is twice the bank size */ size = 2 * size; } #endif #ifdef CONFIG_SDRAM_ECC ecc_init(0, size); #endif /* * OK, size detected -> all done */ return size; } } return 0; /* nothing found ! */ }
static void sdram_tr1_set(int ram_address, int* tr1_value) { int i; int j, k; volatile unsigned int* ram_pointer = (unsigned int *)ram_address; int first_good = -1, last_bad = 0x1ff; unsigned long test[NUM_TRIES] = { 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 }; /* go through all possible SDRAM0_TR1[RDCT] values */ for (i=0; i<=0x1ff; i++) { /* set the current value for TR1 */ mtsdram(SDRAM0_TR1, (0x80800800 | i)); /* write values */ for (j=0; j<NUM_TRIES; j++) { ram_pointer[j] = test[j]; /* clear any cache at ram location */ __asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); } /* read values back */ for (j=0; j<NUM_TRIES; j++) { for (k=0; k<NUM_READS; k++) { /* clear any cache at ram location */ __asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); if (ram_pointer[j] != test[j]) break; } /* read error */ if (k != NUM_READS) break; } /* we have a SDRAM0_TR1[RDCT] that is part of the window */ if (j == NUM_TRIES) { if (first_good == -1) first_good = i; /* found beginning of window */ } else { /* bad read */ /* if we have not had a good read then don't care */ if (first_good != -1) { /* first failure after a good read */ last_bad = i-1; break; } } } /* return the current value for TR1 */ *tr1_value = (first_good + last_bad) / 2; }
/* * Autodetect onboard SDRAM on 405 platforms */ phys_size_t initdram(int board_type) { ulong speed; ulong sdtr1; int i; /* * Determine SDRAM speed */ speed = get_bus_freq(0); /* parameter not used on ppc4xx */ /* * sdtr1 (register SDRAM0_TR) must take into account timings listed * in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into * account actual SDRAM size. So we can set up sdtr1 according to what * is specified in board configuration file while rtr dependds on SDRAM * size we are assuming before detection. */ sdtr1 = compute_sdtr1(speed); for (i=0; i<N_MB0CF; i++) { /* * Disable memory controller. */ mtsdram(SDRAM0_CFG, 0x00000000); /* * Set MB0CF for bank 0. */ mtsdram(SDRAM0_B0CR, mb0cf[i].reg); mtsdram(SDRAM0_TR, sdtr1); mtsdram(SDRAM0_RTR, compute_rtr(speed, mb0cf[i].rows, 64)); udelay(200); /* * Set memory controller options reg, MCOPT1. * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst * read/prefetch. */ mtsdram(SDRAM0_CFG, 0x80800000); udelay(10000); if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) { phys_size_t size = mb0cf[i].size; /* * OK, size detected. Enable second bank if * defined (assumes same type as bank 0) */ #ifdef CONFIG_SDRAM_BANK1 mtsdram(SDRAM0_CFG, 0x00000000); mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg); mtsdram(SDRAM0_CFG, 0x80800000); udelay(10000); /* * Check if 2nd bank is really available. * If the size not equal to the size of the first * bank, then disable the 2nd bank completely. */ if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) != mb0cf[i].size) { mtsdram(SDRAM0_B1CR, 0); mtsdram(SDRAM0_CFG, 0); } else { /* * We have two identical banks, so the size * is twice the bank size */ size = 2 * size; } #endif /* * OK, size detected -> all done */ return size; } } return 0; }
long int spd_sdram(int(read_spd)(uint addr)) { int tmp,row,col; int total_size,bank_size,bank_code; int mode; int bank_cnt; int sdram0_pmit=0x07c00000; int sdram0_b0cr; int sdram0_b1cr = 0; #ifndef CONFIG_405EP /* not on PPC405EP */ int sdram0_b2cr = 0; int sdram0_b3cr = 0; int sdram0_besr0 = -1; int sdram0_besr1 = -1; int sdram0_eccesr = -1; int sdram0_ecccfg; int ecc_on; #endif int sdram0_rtr=0; int sdram0_tr=0; int sdram0_cfg=0; int t_rp; int t_rcd; int t_ras; int t_rc; int min_cas; PPC4xx_SYS_INFO sys_info; unsigned long bus_period_x_10; /* * get the board info */ get_sys_info(&sys_info); bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); if (read_spd == 0){ read_spd=spd_read; /* * Make sure I2C controller is initialized * before continuing. */ i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); } /* Make shure we are using SDRAM */ if (read_spd(2) != 0x04) { SPD_ERR("SDRAM - non SDRAM memory module found\n"); } /* ------------------------------------------------------------------ * configure memory timing register * * data from DIMM: * 27 IN Row Precharge Time ( t RP) * 29 MIN RAS to CAS Delay ( t RCD) * 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS * -------------------------------------------------------------------*/ /* * first figure out which cas latency mode to use * use the min supported mode */ tmp = read_spd(127) & 0x6; if (tmp == 0x02) { /* only cas = 2 supported */ min_cas = 2; /* t_ck = read_spd(9); */ /* t_ac = read_spd(10); */ } else if (tmp == 0x04) { /* only cas = 3 supported */ min_cas = 3; /* t_ck = read_spd(9); */ /* t_ac = read_spd(10); */ } else if (tmp == 0x06) { /* 2,3 supported, so use 2 */ min_cas = 2; /* t_ck = read_spd(23); */ /* t_ac = read_spd(24); */ } else { SPD_ERR("SDRAM - unsupported CAS latency \n"); } /* get some timing values, t_rp,t_rcd,t_ras,t_rc */ t_rp = read_spd(27); t_rcd = read_spd(29); t_ras = read_spd(30); t_rc = t_ras + t_rp; /* The following timing calcs subtract 1 before deviding. * this has effect of using ceiling instead of floor rounding, * and also subtracting 1 to convert number to reg value */ /* set up CASL */ sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT; /* set up PTA */ sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT; /* set up CTP */ tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3; if (tmp < 1) tmp = 1; sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT; /* set LDF = 2 cycles, reg value = 1 */ sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT; /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */ tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3; if (tmp < 0) tmp = 0; if (tmp > 6) tmp = 6; sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT; /* set RCD = t_rcd/bus_period*/ sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ; /*------------------------------------------------------------------ * configure RTR register * -------------------------------------------------------------------*/ row = read_spd(3); col = read_spd(4); tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */ switch (tmp) { case 0x00: tmp = 15625; break; case 0x01: tmp = 15625 / 4; break; case 0x02: tmp = 15625 / 2; break; case 0x03: tmp = 15625 * 2; break; case 0x04: tmp = 15625 * 4; break; case 0x05: tmp = 15625 * 8; break; default: SPD_ERR("SDRAM - Bad refresh period \n"); } /* convert from nsec to bus cycles */ tmp = (tmp * 10) / bus_period_x_10; sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT; /*------------------------------------------------------------------ * determine the number of banks used * -------------------------------------------------------------------*/ /* byte 7:6 is module data width */ if (read_spd(7) != 0) SPD_ERR("SDRAM - unsupported module width\n"); tmp = read_spd(6); if (tmp < 32) SPD_ERR("SDRAM - unsupported module width\n"); else if (tmp < 64) bank_cnt = 1; /* one bank per sdram side */ else if (tmp < 73) bank_cnt = 2; /* need two banks per side */ else if (tmp < 161) bank_cnt = 4; /* need four banks per side */ else SPD_ERR("SDRAM - unsupported module width\n"); /* byte 5 is the module row count (refered to as dimm "sides") */ tmp = read_spd(5); if (tmp == 1) ; else if (tmp==2) bank_cnt *= 2; else if (tmp==4) bank_cnt *= 4; else bank_cnt = 8; /* 8 is an error code */ if (bank_cnt > 4) /* we only have 4 banks to work with */ SPD_ERR("SDRAM - unsupported module rows for this width\n"); #ifndef CONFIG_405EP /* not on PPC405EP */ /* now check for ECC ability of module. We only support ECC * on 32 bit wide devices with 8 bit ECC. */ if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) { sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT; ecc_on = 1; } else { sdram0_ecccfg = 0; ecc_on = 0; } #endif /*------------------------------------------------------------------ * calculate total size * -------------------------------------------------------------------*/ /* calculate total size and do sanity check */ tmp = read_spd(31); total_size = 1 << 22; /* total_size = 4MB */ /* now multiply 4M by the smallest device row density */ /* note that we don't support asymetric rows */ while (((tmp & 0x0001) == 0) && (tmp != 0)) { total_size = total_size << 1; tmp = tmp >> 1; } total_size *= read_spd(5); /* mult by module rows (dimm sides) */ /*------------------------------------------------------------------ * map rows * cols * banks to a mode * -------------------------------------------------------------------*/ switch (row) { case 11: switch (col) { case 8: mode=4; /* mode 5 */ break; case 9: case 10: mode=0; /* mode 1 */ break; default: SPD_ERR("SDRAM - unsupported mode\n"); } break; case 12: switch (col) { case 8: mode=3; /* mode 4 */ break; case 9: case 10: mode=1; /* mode 2 */ break; default: SPD_ERR("SDRAM - unsupported mode\n"); } break; case 13: switch (col) { case 8: mode=5; /* mode 6 */ break; case 9: case 10: if (read_spd(17) == 2) mode = 6; /* mode 7 */ else mode = 2; /* mode 3 */ break; case 11: mode = 2; /* mode 3 */ break; default: SPD_ERR("SDRAM - unsupported mode\n"); } break; default: SPD_ERR("SDRAM - unsupported mode\n"); } /*------------------------------------------------------------------ * using the calculated values, compute the bank * config register values. * -------------------------------------------------------------------*/ /* compute the size of each bank */ bank_size = total_size / bank_cnt; /* convert bank size to bank size code for ppc4xx by takeing log2(bank_size) - 22 */ tmp = bank_size; /* start with tmp = bank_size */ bank_code = 0; /* and bank_code = 0 */ while (tmp > 1) { /* this takes log2 of tmp */ bank_code++; /* and stores result in bank_code */ tmp = tmp >> 1; } /* bank_code is now log2(bank_size) */ bank_code -= 22; /* subtract 22 to get the code */ tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1; sdram0_b0cr = (bank_size * 0) | tmp; #ifndef CONFIG_405EP /* not on PPC405EP */ if (bank_cnt > 1) sdram0_b2cr = (bank_size * 1) | tmp; if (bank_cnt > 2) sdram0_b1cr = (bank_size * 2) | tmp; if (bank_cnt > 3) sdram0_b3cr = (bank_size * 3) | tmp; #else /* PPC405EP chip only supports two SDRAM banks */ if (bank_cnt > 1) sdram0_b1cr = (bank_size * 1) | tmp; if (bank_cnt > 2) total_size = 2 * bank_size; #endif /* * enable sdram controller DCE=1 * enable burst read prefetch to 32 bytes BRPF=2 * leave other functions off */ /*------------------------------------------------------------------ * now that we've done our calculations, we are ready to * program all the registers. * -------------------------------------------------------------------*/ /* disable memcontroller so updates work */ mtsdram(SDRAM0_CFG, 0); #ifndef CONFIG_405EP /* not on PPC405EP */ mtsdram(SDRAM0_BESR0, sdram0_besr0); mtsdram(SDRAM0_BESR1, sdram0_besr1); mtsdram(SDRAM0_ECCCFG, sdram0_ecccfg); mtsdram(SDRAM0_ECCESR, sdram0_eccesr); #endif mtsdram(SDRAM0_RTR, sdram0_rtr); mtsdram(SDRAM0_PMIT, sdram0_pmit); mtsdram(SDRAM0_B0CR, sdram0_b0cr); mtsdram(SDRAM0_B1CR, sdram0_b1cr); #ifndef CONFIG_405EP /* not on PPC405EP */ mtsdram(SDRAM0_B2CR, sdram0_b2cr); mtsdram(SDRAM0_B3CR, sdram0_b3cr); #endif mtsdram(SDRAM0_TR, sdram0_tr); /* SDRAM have a power on delay, 500 micro should do */ udelay(500); sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR; #ifndef CONFIG_405EP /* not on PPC405EP */ if (ecc_on) sdram0_cfg |= SDRAM0_CFG_MEMCHK; #endif mtsdram(SDRAM0_CFG, sdram0_cfg); return (total_size); }
/* * initdram -- 440EPx's DDR controller is a DENALI Core */ int initdram_by_rb(int rows, int banks) { ulong speed = get_bus_freq(0); mtsdram(DDR0_02, 0x00000000); mtsdram(DDR0_00, 0x0000190A); mtsdram(DDR0_01, 0x01000000); mtsdram(DDR0_03, 0x02030602); mtsdram(DDR0_04, 0x0A020200); mtsdram(DDR0_05, 0x02020308); mtsdram(DDR0_06, 0x0102C812); mtsdram(DDR0_07, 0x000D0100); mtsdram(DDR0_08, 0x02430001); mtsdram(DDR0_09, 0x00011D5F); mtsdram(DDR0_10, 0x00000100); mtsdram(DDR0_11, 0x0027C800); mtsdram(DDR0_12, 0x00000003); mtsdram(DDR0_14, 0x00000000); mtsdram(DDR0_17, 0x19000000); mtsdram(DDR0_18, 0x19191919); mtsdram(DDR0_19, 0x19191919); mtsdram(DDR0_20, 0x0B0B0B0B); mtsdram(DDR0_21, 0x0B0B0B0B); mtsdram(DDR0_22, 0x00267F0B); mtsdram(DDR0_23, 0x00000000); mtsdram(DDR0_24, 0x01010002); if (speed > 133333334) mtsdram(DDR0_26, 0x5B26050C); else mtsdram(DDR0_26, 0x5B260408); mtsdram(DDR0_27, 0x0000682B); mtsdram(DDR0_28, 0x00000000); mtsdram(DDR0_31, 0x00000000); mtsdram(DDR0_42, DDR0_42_ADDR_PINS_DECODE(14 - rows) | 0x00000006); mtsdram(DDR0_43, DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) | 0x030A0200); mtsdram(DDR0_44, 0x00000003); mtsdram(DDR0_02, 0x00000001); denali_wait_for_dlllock(); #ifdef CONFIG_DDR_DATA_EYE /* * Perform data eye search if requested. */ denali_core_search_data_eye(); #endif /* * Clear possible errors resulting from data-eye-search. * If not done, then we could get an interrupt later on when * exceptions are enabled. */ set_mcsr(get_mcsr()); return 0; }
/************************************************************************* * * initdram -- 440EPx's DDR controller is a DENALI Core * ************************************************************************/ long int initdram (int board_type) { #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) #if !defined(CONFIG_NAND_SPL) ulong speed = get_bus_freq(0); #else ulong speed = 133333333; /* 133MHz is on the safe side */ #endif mtsdram(DDR0_02, 0x00000000); mtsdram(DDR0_00, 0x0000190A); mtsdram(DDR0_01, 0x01000000); mtsdram(DDR0_03, 0x02030602); mtsdram(DDR0_04, 0x0A020200); mtsdram(DDR0_05, 0x02020308); mtsdram(DDR0_06, 0x0102C812); mtsdram(DDR0_07, 0x000D0100); mtsdram(DDR0_08, 0x02430001); mtsdram(DDR0_09, 0x00011D5F); mtsdram(DDR0_10, 0x00000300); mtsdram(DDR0_11, 0x0027C800); mtsdram(DDR0_12, 0x00000003); mtsdram(DDR0_14, 0x00000000); mtsdram(DDR0_17, 0x19000000); mtsdram(DDR0_18, 0x19191919); mtsdram(DDR0_19, 0x19191919); mtsdram(DDR0_20, 0x0B0B0B0B); mtsdram(DDR0_21, 0x0B0B0B0B); mtsdram(DDR0_22, 0x00267F0B); mtsdram(DDR0_23, 0x00000000); mtsdram(DDR0_24, 0x01010002); if (speed > 133333334) mtsdram(DDR0_26, 0x5B26050C); else mtsdram(DDR0_26, 0x5B260408); mtsdram(DDR0_27, 0x0000682B); mtsdram(DDR0_28, 0x00000000); mtsdram(DDR0_31, 0x00000000); mtsdram(DDR0_42, 0x01000006); mtsdram(DDR0_43, 0x030A0200); mtsdram(DDR0_44, 0x00000003); mtsdram(DDR0_02, 0x00000001); wait_for_dlllock(); #endif /* #ifndef CONFIG_NAND_U_BOOT */ #ifdef CONFIG_DDR_DATA_EYE /* -----------------------------------------------------------+ * Perform data eye search if requested. * ----------------------------------------------------------*/ denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20); #endif return (CFG_MBYTES_SDRAM << 20); }
/************************************************************************* * fixed sdram init -- doesn't use serial presence detect. * * Assumes: 128 MB, non-ECC, non-registered * PLB @ 133 MHz * ************************************************************************/ long int fixed_sdram (void) { uint reg; /*-------------------------------------------------------------------- * Setup some default *------------------------------------------------------------------*/ mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /*-------------------------------------------------------------------- * Setup for board-specific specific mem *------------------------------------------------------------------*/ /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ /* RA=10 RD=3 */ mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ udelay (400); /* Delay 200 usecs (min) */ /*-------------------------------------------------------------------- * Enable the controller, then wait for DCEN to complete *------------------------------------------------------------------*/ mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ for (;;) { mfsdram (mem_mcsts, reg); if (reg & 0x80000000) break; } return (128 * 1024 * 1024); /* 128 MB */ }
/*----------------------------------------------------------------------------- * Function: initdram * Description: Configures SDRAM memory banks for DDR operation. * Auto Memory Configuration option reads the DDR SDRAM EEPROMs * via the IIC bus and then configures the DDR SDRAM memory * banks appropriately. If Auto Memory Configuration is * not used, it is assumed that no DIMM is plugged *-----------------------------------------------------------------------------*/ phys_size_t initdram(int board_type) { unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; unsigned long dimm_ranks[MAXDIMMS]; unsigned long ranks; unsigned long rows; unsigned long banks; unsigned long cols; unsigned long width; unsigned long const sdram_freq = get_bus_freq(0); unsigned long const num_dimm_banks = sizeof(iic0_dimm_addr); /* on board dimm banks */ unsigned long cas_latency = 0; /* to quiet initialization warning */ unsigned long dram_size; debug("\nEntering initdram()\n"); /*------------------------------------------------------------------ * Stop the DDR-SDRAM controller. *-----------------------------------------------------------------*/ mtsdram(DDR0_02, DDR0_02_START_ENCODE(0)); /* * Make sure I2C controller is initialized * before continuing. */ /* switch to correct I2C bus */ I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /*------------------------------------------------------------------ * Clear out the serial presence detect buffers. * Perform IIC reads from the dimm. Fill in the spds. * Check to see if the dimm slots are populated *-----------------------------------------------------------------*/ get_spd_info(dimm_ranks, &ranks, iic0_dimm_addr, num_dimm_banks); /*------------------------------------------------------------------ * Check the frequency supported for the dimms plugged. *-----------------------------------------------------------------*/ check_frequency(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); /*------------------------------------------------------------------ * Check and get size information. *-----------------------------------------------------------------*/ get_dimm_size(dimm_ranks, iic0_dimm_addr, num_dimm_banks, &rows, &banks, &cols, &width); /*------------------------------------------------------------------ * Check the voltage type for the dimms plugged. *-----------------------------------------------------------------*/ check_voltage_type(dimm_ranks, iic0_dimm_addr, num_dimm_banks); /*------------------------------------------------------------------ * Program registers for SDRAM controller. *-----------------------------------------------------------------*/ mtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) | DDR0_00_DLL_START_POINT_DECODE(0x0A)); mtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x01) | DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0x00) | DDR0_01_INT_MASK_ENCODE(0xFF)); program_ddr0_03(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq, rows, &cas_latency); program_ddr0_04(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); program_ddr0_05(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); /* * TODO: tFAW not found in SPD. Value of 13 taken from Sequoia * board SDRAM, but may be overly conservative. */ mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) | DDR0_07_TFAW_ENCODE(13) | DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) | DDR0_07_AREFRESH_ENCODE(0)); mtsdram(DDR0_08, DDR0_08_WRLAT_ENCODE(cas_latency - 1) | DDR0_08_TCPD_ENCODE(200) | DDR0_08_DQS_N_EN_ENCODE(0) | DDR0_08_DDRII_ENCODE(1)); mtsdram(DDR0_09, DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(0x00) | DDR0_09_RTT_0_ENCODE(0x1) | DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(0x1D) | DDR0_09_WR_DQS_SHIFT_ENCODE(DQS_OUT_SHIFT - 0x20)); program_ddr0_10(dimm_ranks, ranks); program_ddr0_11(sdram_freq); mtsdram(DDR0_12, DDR0_12_TCKE_ENCODE(3)); mtsdram(DDR0_14, DDR0_14_DLL_BYPASS_MODE_ENCODE(0) | DDR0_14_REDUC_ENCODE(width <= 40 ? 1 : 0) | DDR0_14_REG_DIMM_ENABLE_ENCODE(0)); mtsdram(DDR0_17, DDR0_17_DLL_DQS_DELAY_0_ENCODE(DLL_DQS_DELAY)); mtsdram(DDR0_18, DDR0_18_DLL_DQS_DELAY_4_ENCODE(DLL_DQS_DELAY) | DDR0_18_DLL_DQS_DELAY_3_ENCODE(DLL_DQS_DELAY) | DDR0_18_DLL_DQS_DELAY_2_ENCODE(DLL_DQS_DELAY) | DDR0_18_DLL_DQS_DELAY_1_ENCODE(DLL_DQS_DELAY)); mtsdram(DDR0_19, DDR0_19_DLL_DQS_DELAY_8_ENCODE(DLL_DQS_DELAY) | DDR0_19_DLL_DQS_DELAY_7_ENCODE(DLL_DQS_DELAY) | DDR0_19_DLL_DQS_DELAY_6_ENCODE(DLL_DQS_DELAY) | DDR0_19_DLL_DQS_DELAY_5_ENCODE(DLL_DQS_DELAY)); mtsdram(DDR0_20, DDR0_20_DLL_DQS_BYPASS_3_ENCODE(DLL_DQS_BYPASS) | DDR0_20_DLL_DQS_BYPASS_2_ENCODE(DLL_DQS_BYPASS) | DDR0_20_DLL_DQS_BYPASS_1_ENCODE(DLL_DQS_BYPASS) | DDR0_20_DLL_DQS_BYPASS_0_ENCODE(DLL_DQS_BYPASS)); mtsdram(DDR0_21, DDR0_21_DLL_DQS_BYPASS_7_ENCODE(DLL_DQS_BYPASS) | DDR0_21_DLL_DQS_BYPASS_6_ENCODE(DLL_DQS_BYPASS) | DDR0_21_DLL_DQS_BYPASS_5_ENCODE(DLL_DQS_BYPASS) | DDR0_21_DLL_DQS_BYPASS_4_ENCODE(DLL_DQS_BYPASS)); program_ddr0_22(dimm_ranks, iic0_dimm_addr, num_dimm_banks, width); mtsdram(DDR0_23, DDR0_23_ODT_RD_MAP_CS0_ENCODE(0x0) | DDR0_23_FWC_ENCODE(0)); program_ddr0_24(ranks); program_ddr0_26(sdram_freq); program_ddr0_27(sdram_freq); mtsdram(DDR0_28, DDR0_28_EMRS3_DATA_ENCODE(0x0000) | DDR0_28_EMRS2_DATA_ENCODE(0x0000)); mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000)); mtsdram(DDR0_42, DDR0_42_ADDR_PINS_DECODE(14 - rows) | DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency)); program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq, cols, banks); program_ddr0_44(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); denali_sdram_register_dump(); dram_size = (width >= 64) ? 8 : 4; dram_size *= 1 << cols; dram_size *= banks; dram_size *= 1 << rows; dram_size *= ranks; debug("dram_size = %lu\n", dram_size); /* Start the SDRAM controler */ mtsdram(DDR0_02, DDR0_02_START_ENCODE(1)); denali_wait_for_dlllock(); #if defined(CONFIG_DDR_DATA_EYE) /* * Map the first 1 MiB of memory in the TLB, and perform the data eye * search. */ program_tlb(0, CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE); denali_core_search_data_eye(); denali_sdram_register_dump(); remove_tlb(CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE); #endif #if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, 0); sync(); /* Zero the memory */ debug("Zeroing SDRAM..."); #if defined(CONFIG_SYS_MEM_TOP_HIDE) dcbz_area(CONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS_MEM_TOP_HIDE); #else #error Please define CONFIG_SYS_MEM_TOP_HIDE (see README) in your board config file #endif /* Write modified dcache lines back to memory */ clean_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS_MEM_TOP_HIDE); debug("Completed\n"); sync(); remove_tlb(CONFIG_SYS_SDRAM_BASE, dram_size); #if defined(CONFIG_DDR_ECC) /* * If ECC is enabled, clear and enable interrupts */ if (is_ecc_enabled()) { u32 val; sync(); /* Clear error status */ mfsdram(DDR0_00, val); mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); /* Set 'int_mask' parameter to functionnal value */ mfsdram(DDR0_01, val); mtsdram(DDR0_01, (val & ~DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF); #if defined(CONFIG_DDR_DATA_EYE) /* * Running denali_core_search_data_eye() when ECC is enabled * causes non-ECC machine checks. This clears them. */ print_mcsr(); mtspr(SPRN_MCSR, mfspr(SPRN_MCSR)); print_mcsr(); #endif sync(); } #endif /* defined(CONFIG_DDR_ECC) */ #endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */ program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE); return dram_size; }
/************************************************************************* * * initdram -- 440EPx's DDR controller is a DENALI Core * ************************************************************************/ phys_size_t initdram (int board_type) { #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \ defined(CONFIG_NAND_SPL) ulong speed = get_bus_freq(0); mtsdram(DDR0_02, 0x00000000); mtsdram(DDR0_00, 0x0000190A); mtsdram(DDR0_01, 0x01000000); mtsdram(DDR0_03, 0x02030602); mtsdram(DDR0_04, 0x0A020200); mtsdram(DDR0_05, 0x02020308); mtsdram(DDR0_06, 0x0102C812); mtsdram(DDR0_07, 0x000D0100); mtsdram(DDR0_08, 0x02430001); mtsdram(DDR0_09, 0x00011D5F); mtsdram(DDR0_10, 0x00000100); mtsdram(DDR0_11, 0x0027C800); mtsdram(DDR0_12, 0x00000003); mtsdram(DDR0_14, 0x00000000); mtsdram(DDR0_17, 0x19000000); mtsdram(DDR0_18, 0x19191919); mtsdram(DDR0_19, 0x19191919); mtsdram(DDR0_20, 0x0B0B0B0B); mtsdram(DDR0_21, 0x0B0B0B0B); mtsdram(DDR0_22, 0x00267F0B); mtsdram(DDR0_23, 0x00000000); mtsdram(DDR0_24, 0x01010002); if (speed > 133333334) mtsdram(DDR0_26, 0x5B26050C); else mtsdram(DDR0_26, 0x5B260408); mtsdram(DDR0_27, 0x0000682B); mtsdram(DDR0_28, 0x00000000); mtsdram(DDR0_31, 0x00000000); mtsdram(DDR0_42, 0x01000006); mtsdram(DDR0_43, 0x030A0200); mtsdram(DDR0_44, 0x00000003); mtsdram(DDR0_02, 0x00000001); denali_wait_for_dlllock(); #endif /* #ifndef CONFIG_NAND_U_BOOT */ #ifdef CONFIG_DDR_DATA_EYE /* -----------------------------------------------------------+ * Perform data eye search if requested. * ----------------------------------------------------------*/ denali_core_search_data_eye(); #endif /* * Clear possible errors resulting from data-eye-search. * If not done, then we could get an interrupt later on when * exceptions are enabled. */ set_mcsr(get_mcsr()); return (CONFIG_SYS_MBYTES_SDRAM << 20); }
/* * phys_size_t initdram(int board_type) * * As the name already indicates, this function is called very early * from start.S and configures the SDRAM with fixed values. This is needed, * since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has * not enough free space to implement the complete I2C SPD DDR autodetection * routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM * when booting from NAND flash. * * Note: * As found out by Eugene O'Brien <*****@*****.**>, the fixed * DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM * modules are still plugged in. So it is recommended to remove the DIMM * modules while using the NAND booting code with the fixed SDRAM setup! */ phys_size_t initdram(int board_type) { /* * Soft-reset SDRAM controller. */ mtsdr(SDR0_SRST, SDR0_SRST_DMC); mtsdr(SDR0_SRST, 0x00000000); /* * Disable memory controller. */ mtsdram(SDRAM0_CFG0, 0x00000000); /* * Setup some default */ mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ mtsdram(SDRAM0_B0CR, 0x00082001); mtsdram(SDRAM0_TR0, 0x41094012); mtsdram(SDRAM0_TR1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/ mtsdram(SDRAM0_RTR, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */ mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/ /* * Enable the controller, then wait for DCEN to complete */ mtsdram(SDRAM0_CFG0, 0x80000000); /* DCEN=1, PMUD=0*/ wait_init_complete(); return CONFIG_SYS_MBYTES_SDRAM << 20; }
static void program_ddr0_03(unsigned long dimm_ranks[], unsigned char const iic0_dimm_addr[], unsigned long num_dimm_banks, unsigned long sdram_freq, unsigned long rows, unsigned long *cas_latency) { unsigned long dimm_num; unsigned long cas_index; unsigned long cycle_2_0_clk; unsigned long cycle_3_0_clk; unsigned long cycle_4_0_clk; unsigned long cycle_5_0_clk; unsigned long max_2_0_tcyc_ps = 100; unsigned long max_3_0_tcyc_ps = 100; unsigned long max_4_0_tcyc_ps = 100; unsigned long max_5_0_tcyc_ps = 100; unsigned char cas_available = 0x3C; /* value for DDR2 */ u32 ddr0_03 = DDR0_03_BSTLEN_ENCODE(0x2) | DDR0_03_INITAREF_ENCODE(0x2); unsigned int const tcyc_addr[3] = { 9, 23, 25 }; /*------------------------------------------------------------------ * Get the board configuration info. *-----------------------------------------------------------------*/ debug("sdram_freq = %d\n", sdram_freq); /*------------------------------------------------------------------ * Handle the timing. We need to find the worst case timing of all * the dimm modules installed. *-----------------------------------------------------------------*/ /* loop through all the DIMM slots on the board */ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_ranks[dimm_num]) { unsigned char const cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18); unsigned char cas_mask; cas_available &= cas_bit; for (cas_mask = 0x80; cas_mask; cas_mask >>= 1) { if (cas_bit & cas_mask) break; } debug("cas_bit (SPD byte 18) = %02X, cas_mask = %02X\n", cas_bit, cas_mask); for (cas_index = 0; cas_index < 3; cas_mask >>= 1, cas_index++) { unsigned long cycle_time_ps; if (!(cas_available & cas_mask)) { continue; } cycle_time_ps = get_tcyc(spd_read(iic0_dimm_addr[dimm_num], tcyc_addr[cas_index])); debug("cas_index = %d: cycle_time_ps = %d\n", cas_index, cycle_time_ps); /* * DDR2 devices use the following bitmask for CAS latency: * Bit 7 6 5 4 3 2 1 0 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD */ switch (cas_mask) { case 0x20: max_5_0_tcyc_ps = max(max_5_0_tcyc_ps, cycle_time_ps); break; case 0x10: max_4_0_tcyc_ps = max(max_4_0_tcyc_ps, cycle_time_ps); break; case 0x08: max_3_0_tcyc_ps = max(max_3_0_tcyc_ps, cycle_time_ps); break; case 0x04: max_2_0_tcyc_ps = max(max_2_0_tcyc_ps, cycle_time_ps); break; } } } } debug("cas_available (bit map) = 0x%02X\n", cas_available); /*------------------------------------------------------------------ * Set the SDRAM mode, SDRAM_MMODE *-----------------------------------------------------------------*/ /* add 10 here because of rounding problems */ cycle_2_0_clk = MULDIV64(ONE_BILLION, 1000, max_2_0_tcyc_ps) + 10; cycle_3_0_clk = MULDIV64(ONE_BILLION, 1000, max_3_0_tcyc_ps) + 10; cycle_4_0_clk = MULDIV64(ONE_BILLION, 1000, max_4_0_tcyc_ps) + 10; cycle_5_0_clk = MULDIV64(ONE_BILLION, 1000, max_5_0_tcyc_ps) + 10; debug("cycle_2_0_clk = %d\n", cycle_2_0_clk); debug("cycle_3_0_clk = %d\n", cycle_3_0_clk); debug("cycle_4_0_clk = %d\n", cycle_4_0_clk); debug("cycle_5_0_clk = %d\n", cycle_5_0_clk); if ((cas_available & 0x04) && (sdram_freq <= cycle_2_0_clk)) { *cas_latency = 2; ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x2) | DDR0_03_CASLAT_LIN_ENCODE(0x4); } else if ((cas_available & 0x08) && (sdram_freq <= cycle_3_0_clk)) { *cas_latency = 3; ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x3) | DDR0_03_CASLAT_LIN_ENCODE(0x6); } else if ((cas_available & 0x10) && (sdram_freq <= cycle_4_0_clk)) { *cas_latency = 4; ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x4) | DDR0_03_CASLAT_LIN_ENCODE(0x8); } else if ((cas_available & 0x20) && (sdram_freq <= cycle_5_0_clk)) { *cas_latency = 5; ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x5) | DDR0_03_CASLAT_LIN_ENCODE(0xA); } else { printf("ERROR: Cannot find a supported CAS latency with the " "installed DIMMs.\n"); printf("Only DDR2 DIMMs with CAS latencies of 2.0, 3.0, 4.0, " "and 5.0 are supported.\n"); printf("Make sure the PLB speed is within the supported range " "of the DIMMs.\n"); printf("sdram_freq=%ld cycle2=%ld cycle3=%ld cycle4=%ld " "cycle5=%ld\n\n", sdram_freq, cycle_2_0_clk, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk); spd_ddr_init_hang(); } debug("CAS latency = %d\n", *cas_latency); mtsdram(DDR0_03, ddr0_03); }
/************************************************************************* * sdram_init -- doesn't use serial presence detect. * * Assumes: 256 MB, ECC, non-registered * PLB @ 133 MHz * ************************************************************************/ void sdram_init(void) { register uint reg; /*-------------------------------------------------------------------- * Setup some default *------------------------------------------------------------------*/ mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ mtsdram(mem_clktr, 0x40000000); /* ?? */ mtsdram(mem_wddctr, 0x40000000); /* ?? */ /*clear this first, if the DDR is enabled by a debugger then you can not make changes. */ mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */ /*-------------------------------------------------------------------- * Setup for board-specific specific mem *------------------------------------------------------------------*/ /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */ mtsdram(mem_tr0, 0x410a4012); /* ?? */ mtsdram(mem_tr1, 0x8080080b); /* ?? */ mtsdram(mem_rtr, 0x04080000); /* ?? */ mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */ udelay(400); /* Delay 200 usecs (min) */ /*-------------------------------------------------------------------- * Enable the controller, then wait for DCEN to complete *------------------------------------------------------------------*/ mtsdram(mem_cfg0, 0x84000000); /* Enable */ for (;;) { mfsdram(mem_mcsts, reg); if (reg & 0x80000000) break; } }
static void program_ddr0_04(unsigned long dimm_ranks[], unsigned char const iic0_dimm_addr[], unsigned long num_dimm_banks, unsigned long sdram_freq) { unsigned long dimm_num; unsigned long t_rc_ps = 0; unsigned long t_rrd_ps = 0; unsigned long t_rtp_ps = 0; unsigned long t_rc_clk; unsigned long t_rrd_clk; unsigned long t_rtp_clk; /*------------------------------------------------------------------ * Handle the timing. We need to find the worst case timing of all * the dimm modules installed. *-----------------------------------------------------------------*/ /* loop through all the DIMM slots on the board */ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_ranks[dimm_num]) { unsigned long ps; /* tRC */ ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 41); switch (spd_read(iic0_dimm_addr[dimm_num], 40) >> 4) { case 0x1: ps += 250; break; case 0x2: ps += 333; break; case 0x3: ps += 500; break; case 0x4: ps += 667; break; case 0x5: ps += 750; break; } t_rc_ps = max(t_rc_ps, ps); /* tRRD */ ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 28); t_rrd_ps = max(t_rrd_ps, ps); /* tRTP */ ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 38); t_rtp_ps = max(t_rtp_ps, ps); } } debug("t_rc_ps = %d\n", t_rc_ps); t_rc_clk = (MULDIV64(sdram_freq, t_rc_ps, ONE_BILLION) + 999) / 1000; debug("t_rrd_ps = %d\n", t_rrd_ps); t_rrd_clk = (MULDIV64(sdram_freq, t_rrd_ps, ONE_BILLION) + 999) / 1000; debug("t_rtp_ps = %d\n", t_rtp_ps); t_rtp_clk = (MULDIV64(sdram_freq, t_rtp_ps, ONE_BILLION) + 999) / 1000; mtsdram(DDR0_04, DDR0_04_TRC_ENCODE(t_rc_clk) | DDR0_04_TRRD_ENCODE(t_rrd_clk) | DDR0_04_TRTP_ENCODE(t_rtp_clk)); }
/************************************************************************* * fixed sdram init -- doesn't use serial presence detect. * * Assumes: 128 MB, non-ECC, non-registered * PLB @ 133 MHz * ************************************************************************/ long int fixed_sdram (void) { uint reg; /*-------------------------------------------------------------------- * Setup some default *------------------------------------------------------------------*/ mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /*-------------------------------------------------------------------- * Setup for board-specific specific mem *------------------------------------------------------------------*/ /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ /* RA=10 RD=3 */ mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ udelay (400); /* Delay 200 usecs (min) */ /*-------------------------------------------------------------------- * Enable the controller, then wait for DCEN to complete *------------------------------------------------------------------*/ mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ for (;;) { mfsdram (SDRAM0_MCSTS, reg); if (reg & 0x80000000) break; } return (128 * 1024 * 1024); /* 128 MB */ }
/************************************************************************* * * initdram -- 440EPx's DDR controller is a DENALI Core * ************************************************************************/ phys_size_t initdram (int board_type) { #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_LCD4_LWMON5) /* CL=4 */ mtsdram(DDR0_02, 0x00000000); mtsdram(DDR0_00, 0x0000190A); mtsdram(DDR0_01, 0x01000000); mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */ mtsdram(DDR0_04, 0x0B030300); mtsdram(DDR0_05, 0x02020308); mtsdram(DDR0_06, 0x0003C812); mtsdram(DDR0_07, 0x00090100); mtsdram(DDR0_08, 0x03c80001); mtsdram(DDR0_09, 0x00011D5F); mtsdram(DDR0_10, 0x00000100); mtsdram(DDR0_11, 0x000CC800); mtsdram(DDR0_12, 0x00000003); mtsdram(DDR0_14, 0x00000000); mtsdram(DDR0_17, 0x1e000000); mtsdram(DDR0_18, 0x1e1e1e1e); mtsdram(DDR0_19, 0x1e1e1e1e); mtsdram(DDR0_20, 0x0B0B0B0B); mtsdram(DDR0_21, 0x0B0B0B0B); #ifdef CONFIG_DDR_ECC mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */ #else mtsdram(DDR0_22, 0x00267F0B); #endif mtsdram(DDR0_23, 0x01000000); mtsdram(DDR0_24, 0x01010001); mtsdram(DDR0_26, 0x2D93028A); mtsdram(DDR0_27, 0x0784682B); mtsdram(DDR0_28, 0x00000080); mtsdram(DDR0_31, 0x00000000); mtsdram(DDR0_42, 0x01000008); mtsdram(DDR0_43, 0x050A0200); mtsdram(DDR0_44, 0x00000005); mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */ denali_wait_for_dlllock(); #if defined(CONFIG_DDR_DATA_EYE) /* -----------------------------------------------------------+ * Perform data eye search if requested. * ----------------------------------------------------------*/ program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20, TLB_WORD2_I_ENABLE); denali_core_search_data_eye(); remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20); #endif /* * Program tlb entries for this size (dynamic) */ program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE); #if defined(CONFIG_DDR_ECC) #if defined(CONFIG_4xx_DCACHE) /* * If ECC is enabled, initialize the parity bits. */ program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0); #else /* CONFIG_4xx_DCACHE */ /* * Setup 2nd TLB with same physical address but different virtual address * with cache enabled. This is done for fast ECC generation. */ program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0); /* * If ECC is enabled, initialize the parity bits. */ program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0); /* * Now after initialization (auto-calibration and ECC generation) * remove the TLB entries with caches enabled and program again with * desired cache functionality */ remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20); #endif /* CONFIG_4xx_DCACHE */ #endif /* CONFIG_DDR_ECC */ /* * Clear possible errors resulting from data-eye-search. * If not done, then we could get an interrupt later on when * exceptions are enabled. */ set_mcsr(get_mcsr()); #endif /* CONFIG_SPL_BUILD */ return (CONFIG_SYS_MBYTES_SDRAM << 20); }