int musb_otg_env_init(void){ u8 power; //u8 intrusb; //step1: mask the PMU/PMIC EINT mtk_musb->usb_if = true; mtk_musb->is_host = true;//workaround for PMIC charger detection //mt65xx_eint_mask(EINT_CHR_DET_NUM); pmic_chrdet_int_en(0); mt_usb_init_drvvbus(); //step5: make sure to power on the USB module if(mtk_musb->power) mtk_musb->power = FALSE; musb_platform_enable(mtk_musb); //step6: clear session bit musb_writeb(mtk_musb->mregs,MUSB_DEVCTL,0); //step7: disable and enable usb interrupt usb_l1intm_store = musb_readl(mtk_musb->mregs,USB_L1INTM); usb_intrrxe_store = musb_readw(mtk_musb->mregs,MUSB_INTRRXE); usb_intrtxe_store = musb_readw(mtk_musb->mregs,MUSB_INTRTXE); usb_intrusbe_store = musb_readb(mtk_musb->mregs,MUSB_INTRUSBE); musb_writel(mtk_musb->mregs,USB_L1INTM,0); musb_writew(mtk_musb->mregs,MUSB_INTRRXE,0); musb_writew(mtk_musb->mregs,MUSB_INTRTXE,0); musb_writeb(mtk_musb->mregs,MUSB_INTRUSBE,0); musb_writew(mtk_musb->mregs,MUSB_INTRRX,0xffff); musb_writew(mtk_musb->mregs,MUSB_INTRTX,0xffff); musb_writeb(mtk_musb->mregs,MUSB_INTRUSB,0xff); free_irq (mtk_musb->nIrq, mtk_musb); musb_writel(mtk_musb->mregs,USB_L1INTM,0x105); musb_writew(mtk_musb->mregs,MUSB_INTRTXE,1); musb_writeb(mtk_musb->mregs,MUSB_INTRUSBE,0xf7); //setp8: set the index to 0 for ep0, maybe no need. Designers said it is better not to use the index register. musb_writeb(mtk_musb->mregs, MUSB_INDEX, 0); //setp9: init message g_otg_message.msg = 0; spin_lock_init(&g_otg_message.lock); init_completion(&stop_event); #ifdef DX_DBG power = musb_readb(mtk_musb->mregs,MUSB_POWER); DBG(0,"start the USB-IF test in EM,power=0x%x!\n",power); #endif return 0; }
static int omap2430_runtime_suspend(struct device *dev) { struct omap2430_glue *glue = dev_get_drvdata(dev); struct musb *musb = glue_to_musb(glue); if (musb) { musb->context.otg_interfsel = musb_readl(musb->mregs, OTG_INTERFSEL); omap2430_low_level_exit(musb); } return 0; }
static int omap2430_musb_init(struct musb *musb) { u32 l, status = 0; struct device *dev = musb->controller; struct musb_hdrc_platform_data *plat = dev->platform_data; struct omap_musb_board_data *data = plat->board_data; /* We require some kind of external transceiver, hooked * up through ULPI. TWL4030-family PMICs include one, * which needs a driver, drivers aren't always needed. */ musb->xceiv = otg_get_transceiver(); if (!musb->xceiv) { pr_err("HS USB OTG: no transceiver configured\n"); return -ENODEV; } status = pm_runtime_get_sync(dev); if (status < 0) { dev_err(dev, "pm_runtime_get_sync FAILED"); goto err1; } l = musb_readl(musb->mregs, OTG_INTERFSEL); if (data->interface_type == MUSB_INTERFACE_UTMI) { /* OMAP4 uses Internal PHY GS70 which uses UTMI interface */ l &= ~ULPI_12PIN; /* Disable ULPI */ l |= UTMI_8BIT; /* Enable UTMI */ } else { l |= ULPI_12PIN; } musb_writel(musb->mregs, OTG_INTERFSEL, l); pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, " "sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n", musb_readl(musb->mregs, OTG_REVISION), musb_readl(musb->mregs, OTG_SYSCONFIG), musb_readl(musb->mregs, OTG_SYSSTATUS), musb_readl(musb->mregs, OTG_INTERFSEL), musb_readl(musb->mregs, OTG_SIMENABLE)); musb->nb.notifier_call = musb_otg_notifications; status = otg_register_notifier(musb->xceiv, &musb->nb); if (status) dev_dbg(musb->controller, "notification register failed\n"); setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); return 0; err1: pm_runtime_disable(dev); return status; }
static int musb_platform_resume(struct musb *musb) { u32 l; if (!musb->clock) return 0; otg_set_suspend(musb->xceiv, 0); if (musb->set_clock) musb->set_clock(musb->clock, 1); else clk_enable(musb->clock); l = musb_readl(musb->mregs, OTG_SYSCONFIG); l &= ~ENABLEWAKEUP; /* disable wakeup */ musb_writel(musb->mregs, OTG_SYSCONFIG, l); l = musb_readl(musb->mregs, OTG_FORCESTDBY); l &= ~ENABLEFORCE; /* disable MSTANDBY */ musb_writel(musb->mregs, OTG_FORCESTDBY, l); return 0; }
static void tusb_omap_dma_release(struct dma_channel *channel) { struct tusb_omap_dma_ch *chdat = to_chdat(channel); struct musb *musb = chdat->musb; void __iomem *tbase = musb->ctrl_base; u32 reg; dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum, chdat->ch); reg = musb_readl(tbase, TUSB_DMA_INT_MASK); if (chdat->tx) reg |= (1 << chdat->epnum); else reg |= (1 << (chdat->epnum + 15)); musb_writel(tbase, TUSB_DMA_INT_MASK, reg); reg = musb_readl(tbase, TUSB_DMA_INT_CLEAR); if (chdat->tx) reg |= (1 << chdat->epnum); else reg |= (1 << (chdat->epnum + 15)); musb_writel(tbase, TUSB_DMA_INT_CLEAR, reg); channel->status = MUSB_DMA_STATUS_UNKNOWN; if (chdat->ch >= 0) { omap_stop_dma(chdat->ch); omap_free_dma(chdat->ch); chdat->ch = -1; } if (chdat->dmareq >= 0) tusb_omap_dma_free_dmareq(chdat); channel = NULL; }
void musb_link_force_active(int enable) { if ( LGMUSB_P == NULL ) { printk(KERN_ERR "<<<<<<<<<<<<<< LGMUSB_P can not get musb address\n"); return; } u32 l; l = musb_readl(LGMUSB_P->mregs, OTG_SYSCONFIG); if (enable) { l &= ~SMARTSTDBY; l |= NOSTDBY; l &= ~SMARTIDLE; l |= NOIDLE; musb_writel(LGMUSB_P->mregs, OTG_FORCESTDBY, (musb_readl(LGMUSB_P->mregs,OTG_FORCESTDBY) & ~ENABLEFORCE)); } else { l |= ENABLEWAKEUP; l &= ~SMARTSTDBY; l |= FORCESTDBY; l &= ~NOSTDBY; l |= FORCEIDLE; l &= ~NOIDLE; musb_writel(LGMUSB_P->mregs, OTG_FORCESTDBY, (musb_readl(LGMUSB_P->mregs,OTG_FORCESTDBY) | ENABLEFORCE)); } musb_writel(LGMUSB_P->mregs, OTG_SYSCONFIG, l); }
static int omap2430_musb_init(struct musb *musb) { u32 l; int status = 0; struct device *dev = musb->controller; struct musb_hdrc_platform_data *plat = dev->platform_data; struct omap_musb_board_data *data = plat->board_data; musb->xceiv = usb_get_transceiver(); if (!musb->xceiv) { pr_err("HS USB OTG: no transceiver configured\n"); return -ENODEV; } INIT_WORK(&musb->otg_notifier_work, musb_otg_notifier_work); status = pm_runtime_get_sync(dev); if (status < 0) { dev_err(dev, "pm_runtime_get_sync FAILED %d\n", status); goto err1; } l = musb_readl(musb->mregs, OTG_INTERFSEL); if (data->interface_type == MUSB_INTERFACE_UTMI) { l &= ~ULPI_12PIN; l |= UTMI_8BIT; } else { l |= ULPI_12PIN; } musb_writel(musb->mregs, OTG_INTERFSEL, l); pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, " "sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n", musb_readl(musb->mregs, OTG_REVISION), musb_readl(musb->mregs, OTG_SYSCONFIG), musb_readl(musb->mregs, OTG_SYSSTATUS), musb_readl(musb->mregs, OTG_INTERFSEL), musb_readl(musb->mregs, OTG_SIMENABLE)); musb->nb.notifier_call = musb_otg_notifications; status = usb_register_notifier(musb->xceiv, &musb->nb); if (status) dev_dbg(musb->controller, "notification register failed\n"); setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); pm_runtime_put_noidle(musb->controller); return 0; err1: return status; }
static void cppi41_autoreq_update(struct cppi41_channel *rx_ch, u8 autoreq) { struct cppi41 *cppi = rx_ch->channel.private_data; if (is_host_active(cppi->musb) && autoreq != rx_ch->autoreq) { void *__iomem reg_base = cppi->musb->ctrl_base; u32 reg_val = musb_readl(reg_base, cppi->automode_reg_offs); u8 ep_num = rx_ch->ch_num + 1; reg_val &= ~USB_RX_AUTOREQ_MASK(ep_num); reg_val |= autoreq << USB_RX_AUTOREQ_SHIFT(ep_num); musb_writel(reg_base, cppi->automode_reg_offs, reg_val); rx_ch->autoreq = autoreq; }
void musb_platform_try_idle(struct musb *musb, unsigned long timeout) { unsigned long default_timeout = jiffies + msecs_to_jiffies(3); static unsigned long last_timer; u32 val; if (timeout == 0) timeout = default_timeout; /* Never idle if active, or when VBUS timeout is not set as host */ if (musb->is_active || ((musb->a_wait_bcon == 0) && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) { DBG(4, "%s active, deleting timer\n", otg_state_string(musb)); del_timer(&musb_idle_timer); last_timer = jiffies; return; } if (musb->xceiv->state == OTG_STATE_UNDEFINED) { /* disable the phy clock when the gadget driver is unloaded. * Powerdown the phy and configure the musb sysconfig to * force standby/idle. * this will allow the core to hit retention and offmode */ otg_shutdown(musb->xceiv); /* configure in force idle/ standby */ val = musb_readl(musb->mregs, OTG_SYSCONFIG); val &= ~(SMARTIDLEWKUP | SMARTSTDBY | NOSTDBY | ENABLEWAKEUP); val |= FORCEIDLE | FORCESTDBY; musb_writel(musb->mregs, OTG_SYSCONFIG, val); musb_writel(musb->mregs, OTG_FORCESTDBY, 1); } if (time_after(last_timer, timeout)) { if (!timer_pending(&musb_idle_timer)) last_timer = timeout; else { DBG(4, "Longer idle timer already pending, ignoring\n"); return; } } last_timer = timeout; DBG(4, "%s inactive, for idle timer for %lu ms\n", otg_state_string(musb), (unsigned long)jiffies_to_msecs(timeout - jiffies)); mod_timer(&musb_idle_timer, timeout); }
int __init musb_platform_init(struct musb *musb) { void __iomem *tibase = musb->ctrl_base; u32 revision; musb->mregs += DAVINCI_BASE_OFFSET; #if 0 /* REVISIT there's something odd about clocking, this * didn't appear do the job ... */ musb->clock = clk_get(pDevice, "usb"); if (IS_ERR(musb->clock)) return PTR_ERR(musb->clock); status = clk_enable(musb->clock); if (status < 0) return -ENODEV; #endif /* returns zero if e.g. not clocked */ revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG); if (revision == 0) return -ENODEV; if (is_host_enabled(musb)) setup_timer(&otg_workaround, otg_timer, (unsigned long) musb); musb->board_set_vbus = davinci_set_vbus; davinci_source_power(musb, 0, 1); /* reset the controller */ musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1); /* start the on-chip PHY and its PLL */ phy_on(); msleep(5); /* NOTE: irqs are in mixed mode, not bypass to pure-musb */ pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n", revision, __raw_readl((void __force __iomem *) IO_ADDRESS(USBPHY_CTL_PADDR)), musb_readb(tibase, DAVINCI_USB_CTRL_REG)); musb->isr = davinci_interrupt; return 0; }
int __init musb_platform_init(struct musb *musb) { int err; #ifdef CONFIG_USB_MTK_HDRC_HCD if (is_host_enabled(musb)) { musb->board_set_vbus = mtk_set_vbus; //<2013/03/27-23263-stevenchen, Correct GPIO12 & GPIO38 configuration to low down standby current. #ifndef CONFIG_MT6589_FPGA #ifndef MTK_BQ24196_SUPPORT #ifndef MTK_BQ24157_SUPPORT mt_set_gpio_mode(GPIO_OTG_DRVVBUS_PIN,GPIO_OTG_DRVVBUS_PIN_M_GPIO);//should set GPIO2 as gpio mode. mt_set_gpio_dir(GPIO_OTG_DRVVBUS_PIN,GPIO_DIR_OUT); mt_get_gpio_pull_enable(GPIO_OTG_DRVVBUS_PIN); mt_set_gpio_pull_select(GPIO_OTG_DRVVBUS_PIN,GPIO_PULL_UP); #endif #endif #endif //>2013/03/27-23263-stevenchen } #endif musb->nIrq = MT6589_USB0_IRQ_ID; musb->dma_irq= (int)SHARE_IRQ; musb->fifo_cfg = fifo_cfg; musb->fifo_cfg_size = ARRAY_SIZE(fifo_cfg); musb->fifo_cfg_host = fifo_cfg_host; musb->fifo_cfg_host_size = ARRAY_SIZE(fifo_cfg_host); mtk_musb->power = FALSE; mtk_musb->is_host = FALSE; mtk_musb->fifo_size = 8*1024; #ifndef CONFIG_MT6589_FPGA hwPowerOn(MT65XX_POWER_LDO_VUSB, VOL_3300, "VUSB_LDO"); printk("%s, enable VBUS_LDO \n", __func__); #endif musb_platform_enable(musb); emi_mpu_notifier_register(MST_ID_MMPERI_1, musb_check_mpu_violation); musb->isr = mt_usb_interrupt; musb_writel(musb->mregs,MUSB_HSDMA_INTR,0xff | (0xff << DMA_INTR_UNMASK_SET_OFFSET)); DBG(2,"musb platform init %x\n",musb_readl(musb->mregs,MUSB_HSDMA_INTR)); musb_writel(musb->mregs,USB_L1INTM,TX_INT_STATUS | RX_INT_STATUS | USBCOM_INT_STATUS | DMA_INT_STATUS); err = device_create_file(musb->controller,&dev_attr_cmode); return 0; }
static int dsps_musb_set_mode(struct musb *musb, u8 mode) { struct device *dev = musb->controller; struct dsps_glue *glue = dev_get_drvdata(dev->parent); const struct dsps_musb_wrapper *wrp = glue->wrp; void __iomem *ctrl_base = musb->ctrl_base; u32 reg; reg = musb_readl(ctrl_base, wrp->mode); switch (mode) { case MUSB_HOST: reg &= ~(1 << wrp->iddig); /* * if we're setting mode to host-only or device-only, we're * going to ignore whatever the PHY sends us and just force * ID pin status by SW */ reg |= (1 << wrp->iddig_mux); musb_writel(ctrl_base, wrp->mode, reg); musb_writel(ctrl_base, wrp->phy_utmi, 0x02); break; case MUSB_PERIPHERAL: reg |= (1 << wrp->iddig); /* * if we're setting mode to host-only or device-only, we're * going to ignore whatever the PHY sends us and just force * ID pin status by SW */ reg |= (1 << wrp->iddig_mux); musb_writel(ctrl_base, wrp->mode, reg); break; case MUSB_OTG: musb_writel(ctrl_base, wrp->phy_utmi, 0x02); break; default: dev_err(glue->dev, "unsupported mode %d\n", mode); return -EINVAL; } return 0; }
static int omap2430_runtime_suspend(struct device *dev) { struct omap2430_glue *glue = dev_get_drvdata(dev); struct musb *musb = glue_to_musb(glue); if (mutex_trylock(&musb->musb_lock)) { dev_info(dev, "runtime suspend\n"); musb->context.otg_interfsel = musb_readl(musb->mregs, OTG_INTERFSEL); omap2430_low_level_exit(musb); otg_set_suspend(musb->xceiv, 1); mutex_unlock(&musb->musb_lock); return 0; } return -EBUSY; }
static int am35x_musb_init(struct musb *musb) { struct device *dev = musb->controller; struct musb_hdrc_platform_data *plat = dev->platform_data; struct omap_musb_board_data *data = plat->board_data; void __iomem *reg_base = musb->ctrl_base; u32 rev; musb->mregs += USB_MENTOR_CORE_OFFSET; /* Returns zero if e.g. not clocked */ rev = musb_readl(reg_base, USB_REVISION_REG); if (!rev) return -ENODEV; usb_nop_xceiv_register(); musb->xceiv = otg_get_transceiver(); if (!musb->xceiv) return -ENODEV; if (is_host_enabled(musb)) setup_timer(&otg_workaround, otg_timer, (unsigned long) musb); /* Reset the musb */ if (data->reset) data->reset(); /* Reset the controller */ musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK); /* Start the on-chip PHY and its PLL. */ if (data->set_phy_power) data->set_phy_power(1); msleep(5); musb->isr = am35x_musb_interrupt; /* clear level interrupt */ if (data->clear_irq) data->clear_irq(); return 0; }
void musb_platform_enable(struct musb *musb) { unsigned long flags; printk("%s, %d, %d\n", __func__, mtk_usb_power, musb->power); if (musb->power == true) return; flags = musb_readl(mtk_musb->mregs,USB_L1INTM); // mask ID pin, so "open clock" and "set flag" won't be interrupted. ISR may call clock_disable. musb_writel(mtk_musb->mregs,USB_L1INTM,(~IDDIG_INT_STATUS)&flags); if (platform_init_first) { DBG(0,"usb init first\n\r"); musb->is_host = true; } if (!mtk_usb_power) { if (down_interruptible(&power_clock_lock)) xlog_printk(ANDROID_LOG_ERROR, "USB20", "%s: busy, Couldn't get power_clock_lock\n" \ , __func__); #ifndef CONFIG_MT6575T_FPGA enable_pll(MT65XX_UPLL, "USB_PLL"); hwPowerOn(MT65XX_POWER_LDO_VUSB, VOL_3300, "VUSB_LDO"); printk("%s, enable VUSB and UPLL before connect\n", __func__); #endif mdelay(10); usb_phy_recover(); mtk_usb_power = true; up(&power_clock_lock); } musb->power = true; musb_writel(mtk_musb->mregs,USB_L1INTM,flags); }
/* * Allocate dmareq0 to the current channel unless it's already taken */ static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat) { u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); if (reg != 0) { dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n", chdat->epnum, reg & 0xf); return -EAGAIN; } if (chdat->tx) reg = (1 << 4) | chdat->epnum; else reg = chdat->epnum; musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); return 0; }
/* Context: controller irqlocked */ static inline void cppi_rndis_update(struct cppi_channel *c, int is_rx, void __iomem *tibase, int is_rndis) { /* we may need to change the rndis flag for this cppi channel */ if (c->is_rndis != is_rndis) { u32 value = musb_readl(tibase, DAVINCI_RNDIS_REG); u32 temp = 1 << (c->index); if (is_rx) temp <<= 16; if (is_rndis) value |= temp; else value &= ~temp; musb_writel(tibase, DAVINCI_RNDIS_REG, value); c->is_rndis = is_rndis; } }
static int musb_platform_suspend(struct musb *musb) { u32 l; struct device *dev = musb->controller; struct musb_hdrc_platform_data *pdata = dev->platform_data; struct omap_hwmod *oh = pdata->oh; if (!musb->clock) return 0; /* in any role */ l = musb_readl(musb->mregs, OTG_FORCESTDBY); l |= ENABLEFORCE; /* enable MSTANDBY */ musb_writel(musb->mregs, OTG_FORCESTDBY, l); pdata->enable_wakeup(oh->od); otg_set_suspend(musb->xceiv, 1); return 0; }
void static otg_int_init(void) { #ifdef ID_PIN_USE_EX_EINT mt_set_gpio_mode(GPIO_OTG_IDDIG_EINT_PIN, GPIO_OTG_IDDIG_EINT_PIN_M_USB_IDDIG); mt_set_gpio_dir(GPIO_OTG_IDDIG_EINT_PIN, GPIO_DIR_IN); mt_set_gpio_pull_enable(GPIO_OTG_IDDIG_EINT_PIN, GPIO_PULL_ENABLE); mt_set_gpio_pull_select(GPIO_OTG_IDDIG_EINT_PIN, GPIO_PULL_UP); mt_eint_set_sens(IDDIG_EINT_PIN, MT_LEVEL_SENSITIVE); mt_eint_set_hw_debounce(IDDIG_EINT_PIN,64); mt_eint_registration(IDDIG_EINT_PIN, EINTF_TRIGGER_LOW, mt_usb_ext_iddig_int, FALSE); #else u32 phy_id_pull = 0; phy_id_pull = __raw_readl(U2PHYDTM1); phy_id_pull |= ID_PULL_UP; __raw_writel(phy_id_pull,U2PHYDTM1); musb_writel(mtk_musb->mregs,USB_L1INTM,IDDIG_INT_STATUS|musb_readl(mtk_musb->mregs,USB_L1INTM)); #endif }
static int musb_platform_resume(struct musb *musb) { u32 l; struct device *dev = musb->controller; struct musb_hdrc_platform_data *pdata = dev->platform_data; struct omap_hwmod *oh = pdata->oh; if (!musb->clock) return 0; otg_set_suspend(musb->xceiv, 0); pm_runtime_enable(dev); pm_runtime_get_sync(dev); pdata->disable_wakeup(oh->od); l = musb_readl(musb->mregs, OTG_FORCESTDBY); l &= ~ENABLEFORCE; /* disable MSTANDBY */ musb_writel(musb->mregs, OTG_FORCESTDBY, l); return 0; }
static int da8xx_musb_init(struct musb *musb) { void __iomem *reg_base = musb->ctrl_base; u32 rev; int ret = -ENODEV; musb->mregs += DA8XX_MENTOR_CORE_OFFSET; /* Returns zero if e.g. not clocked */ rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG); if (!rev) goto fail; usb_nop_xceiv_register(); musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); if (IS_ERR_OR_NULL(musb->xceiv)) { ret = -EPROBE_DEFER; goto fail; } setup_timer(&otg_workaround, otg_timer, (unsigned long)musb); /* Reset the controller */ musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK); /* Start the on-chip PHY and its PLL. */ phy_on(); msleep(5); /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */ pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n", rev, __raw_readl(CFGCHIP2), musb_readb(reg_base, DA8XX_USB_CTRL_REG)); musb->isr = da8xx_musb_interrupt; return 0; fail: return ret; }
void otg_int_init(void) { //bool is_ready = mtk_musb->is_ready; #ifdef ID_PIN_USE_EX_EINT mt_set_gpio_mode(ID_PIN_GPIO, GPIO_ID_PIN_EINT_PIN_M_EINT); mt_set_gpio_dir(ID_PIN_GPIO, GPIO_DIR_IN); mt_set_gpio_pull_enable(ID_PIN_GPIO, GPIO_PULL_ENABLE); mt_set_gpio_pull_select(ID_PIN_GPIO, GPIO_PULL_UP); #else u32 phy_id_pull = 0; phy_id_pull = __raw_readl(U2PHYDTM1); phy_id_pull |= ID_PULL_UP; __raw_writel(phy_id_pull,U2PHYDTM1); #endif //mt65xx_eint_set_sens(ID_PIN_EINT, MT65xx_LEVEL_SENSITIVE); //mt65xx_eint_set_hw_debounce(ID_PIN_EINT,64); //mtk_musb->is_ready = FALSE; //mt65xx_eint_registration(ID_PIN_EINT, FALSE, !DEVICE_INTTERRUPT, musb_id_pin_interrup,FALSE); //mtk_musb->is_ready = is_ready; musb_writel(mtk_musb->mregs,USB_L1INTM,IDDIG_INT_STATUS|musb_readl(mtk_musb->mregs,USB_L1INTM)); }
int __init musb_platform_init(struct musb *musb) { int err; #ifndef CONFIG_MT6575T_FPGA if (is_host_enabled(musb)) { #ifdef CONFIG_USB_MTK_HDRC_HCD musb->board_set_vbus = mtk_set_vbus; mt_set_gpio_mode(GPIO_OTG_DRVVBUS_PIN,GPIO_OTG_DRVVBUS_PIN_M_GPIO);//should set GPIO2 as gpio mode. mt_set_gpio_dir(GPIO_OTG_DRVVBUS_PIN,GPIO_DIR_OUT); mt_get_gpio_pull_enable(GPIO_OTG_DRVVBUS_PIN); mt_set_gpio_pull_select(GPIO_OTG_DRVVBUS_PIN,GPIO_PULL_UP); #endif } #endif musb->nIrq = MT6577_USB0_IRQ_ID; musb->dma_irq= (int)SHARE_IRQ; musb->fifo_cfg = fifo_cfg; musb->fifo_cfg_size = ARRAY_SIZE(fifo_cfg); musb->fifo_cfg_host = fifo_cfg_host; musb->fifo_cfg_host_size = ARRAY_SIZE(fifo_cfg_host); mtk_musb->power = FALSE; mtk_musb->is_host = FALSE; mtk_musb->fifo_size = 8*1024; //mt6575_irq_set_sens(MT6575_USB0_IRQ_ID, MT65xx_LEVEL_SENSITIVE); //mt65xx_irq_set_polarity(MT6575_USB0_IRQ_ID, MT65xx_POLARITY_LOW); musb_platform_enable(musb); musb->isr = mt6577_usb_interrupt; musb_writel(musb->mregs,MUSB_HSDMA_INTR,0xff | (0xff << DMA_INTR_UNMASK_SET_OFFSET)); DBG(2,"musb platform init %x\n",musb_readl(musb->mregs,MUSB_HSDMA_INTR)); musb_writel(musb->mregs,USB_L1INTM,TX_INT_STATUS | RX_INT_STATUS | USBCOM_INT_STATUS | DMA_INT_STATUS); err = device_create_file(musb->controller,&dev_attr_cmode); return 0; }
int musb_qmu_init(struct musb *musb) { /* set DMA channel 0 burst mode to boost QMU speed */ musb_writel(musb->mregs, 0x204, musb_readl(musb->mregs, 0x204) | 0x600); #ifdef CONFIG_OF qmu_base = (void __iomem *)(mtk_musb->mregs + MUSB_QMUBASE); /* debug variable to check qmu_base issue */ qmu_base_2 = (void __iomem *)(mtk_musb->mregs + MUSB_QMUBASE); #else qmu_base = (void __iomem *)(USB_BASE + MUSB_QMUBASE); /* debug variable to check qmu_base issue */ qmu_base_2 = (void __iomem *)(mtk_musb->mregs + MUSB_QMUBASE); #endif mb(); if (qmu_init_gpd_pool(musb->controller)) { QMU_ERR("[QMU]qmu_init_gpd_pool fail\n"); return -1; } return 0; }
/* blocking notifier support */ int musb_notifier_call(struct notifier_block *nb, unsigned long event, void *unused) { struct musb *musb = container_of(nb, struct musb, nb); struct device *dev = musb->controller; struct musb_hdrc_platform_data *pdata = dev->platform_data; struct omap_musb_board_data *data = pdata->board_data; static int hostmode; u32 val; switch (event) { case USB_EVENT_ID: DBG(1, "ID GND\n"); /* configure musb into smartidle with wakeup enabled * smart standby mode. */ musb_writel(musb->mregs, OTG_FORCESTDBY, 0); val = musb_readl(musb->mregs, OTG_SYSCONFIG); if (cpu_is_omap44xx()) val |= SMARTIDLEWKUP | SMARTSTDBY | ENABLEWAKEUP; else val |= SMARTIDLE | SMARTSTDBY | ENABLEWAKEUP; musb_writel(musb->mregs, OTG_SYSCONFIG, val); if (data->interface_type == MUSB_INTERFACE_UTMI) { otg_init(musb->xceiv); hostmode = 1; musb_enable_vbus(musb); } val = __raw_readl(phymux_base + USBA0_OTG_CE_PAD1_USBA0_OTG_DP); val |= DP_WAKEUPENABLE; __raw_writel(val, phymux_base + USBA0_OTG_CE_PAD1_USBA0_OTG_DP); break; case USB_EVENT_VBUS: DBG(1, "VBUS Connect\n"); /* configure musb into smartidle with wakeup enabled * smart standby mode. */ musb_writel(musb->mregs, OTG_FORCESTDBY, 0); val = musb_readl(musb->mregs, OTG_SYSCONFIG); if (cpu_is_omap44xx()) val |= SMARTIDLEWKUP | SMARTSTDBY | ENABLEWAKEUP; else val |= SMARTIDLE | SMARTSTDBY | ENABLEWAKEUP; musb_writel(musb->mregs, OTG_SYSCONFIG, val); if (data->interface_type == MUSB_INTERFACE_UTMI) { otg_init(musb->xceiv); if (!hostmode) { /* Enable VBUS Valid, AValid. Clear SESSEND.*/ __raw_writel(IDDIG | AVALID | VBUSVALID, ctrl_base + USBOTGHS_CONTROL); } } break; case USB_EVENT_NONE: DBG(1, "VBUS Disconnect\n"); if (data->interface_type == MUSB_INTERFACE_UTMI) { /* enable this clock because in suspend interrupt * handler phy clocks are disabled. If phy clocks are * not enabled then DISCONNECT interrupt will not be * reached to mentor */ otg_set_clk(musb->xceiv, 1); __raw_writel(SESSEND | IDDIG, ctrl_base + USBOTGHS_CONTROL); if (musb->xceiv->set_vbus) otg_set_vbus(musb->xceiv, 0); otg_shutdown(musb->xceiv); } hostmode = 0; /* configure in force idle/ standby */ musb_writel(musb->mregs, OTG_FORCESTDBY, 1); val = musb_readl(musb->mregs, OTG_SYSCONFIG); val &= ~(SMARTIDLEWKUP | SMARTSTDBY | ENABLEWAKEUP); val |= FORCEIDLE | FORCESTDBY; musb_writel(musb->mregs, OTG_SYSCONFIG, val); val = __raw_readl(phymux_base + USBA0_OTG_CE_PAD1_USBA0_OTG_DP); val &= ~DP_WAKEUPENABLE; __raw_writel(val, phymux_base + USBA0_OTG_CE_PAD1_USBA0_OTG_DP); break; default: DBG(1, "ID float\n"); return NOTIFY_DONE; } return NOTIFY_OK; }
int __init musb_platform_init(struct musb *musb) { u32 l; struct device *dev = musb->controller; struct musb_hdrc_platform_data *plat = dev->platform_data; struct omap_musb_board_data *data = plat->board_data; int status; u32 val; /* We require some kind of external transceiver, hooked * up through ULPI. TWL4030-family PMICs include one, * which needs a driver, drivers aren't always needed. */ musb->xceiv = otg_get_transceiver(); if (!musb->xceiv) { pr_err("HS USB OTG: no transceiver configured\n"); return -ENODEV; } /* Fixme this can be enabled when load the gadget driver also*/ musb_platform_resume(musb); /*powerup the phy as romcode would have put the phy in some state * which is impacting the core retention if the gadget driver is not * loaded. */ l = musb_readl(musb->mregs, OTG_INTERFSEL); if (data->interface_type == MUSB_INTERFACE_UTMI) { /* OMAP4 uses Internal PHY GS70 which uses UTMI interface */ l &= ~ULPI_12PIN; /* Disable ULPI */ l |= UTMI_8BIT; /* Enable UTMI */ } else { l |= ULPI_12PIN; } musb_writel(musb->mregs, OTG_INTERFSEL, l); pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, " "sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n", musb_readl(musb->mregs, OTG_REVISION), musb_readl(musb->mregs, OTG_SYSCONFIG), musb_readl(musb->mregs, OTG_SYSSTATUS), musb_readl(musb->mregs, OTG_INTERFSEL), musb_readl(musb->mregs, OTG_SIMENABLE)); if (is_host_enabled(musb)) musb->board_set_vbus = omap_set_vbus; setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); plat->is_usb_active = is_musb_active; wake_lock_init(&plat->musb_lock, WAKE_LOCK_SUSPEND, "musb_wake_lock"); if (cpu_is_omap44xx()) { phymux_base = ioremap(0x4A100000, SZ_1K); ctrl_base = ioremap(0x4A002000, SZ_1K); /* register for transciever notification*/ status = otg_register_notifier(musb->xceiv, &musb->nb); if (status) { DBG(1, "notification register failed\n"); wake_lock_destroy(&plat->musb_lock); } ctrl_base = ioremap(0x4A002000, SZ_1K); if (!ctrl_base) { dev_err(dev, "ioremap failed\n"); return -ENOMEM; } } /* configure in force idle/ standby */ musb_writel(musb->mregs, OTG_FORCESTDBY, 1); val = musb_readl(musb->mregs, OTG_SYSCONFIG); val &= ~(SMARTIDLEWKUP | NOSTDBY | ENABLEWAKEUP); val |= FORCEIDLE | FORCESTDBY; musb_writel(musb->mregs, OTG_SYSCONFIG, val); l = musb_readl(musb->mregs, OTG_FORCESTDBY); l &= ~ENABLEFORCE; /* disable MSTANDBY */ musb_writel(musb->mregs, OTG_FORCESTDBY, l); return 0; }
static int davinci_musb_init(struct musb *musb) { void __iomem *tibase = musb->ctrl_base; u32 revision; int ret = -ENODEV; usb_nop_xceiv_register(); musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); if (IS_ERR_OR_NULL(musb->xceiv)) { ret = -EPROBE_DEFER; goto unregister; } musb->mregs += DAVINCI_BASE_OFFSET; /* returns zero if e.g. not clocked */ revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG); if (revision == 0) goto fail; setup_timer(&otg_workaround, otg_timer, (unsigned long) musb); davinci_musb_source_power(musb, 0, 1); /* dm355 EVM swaps D+/D- for signal integrity, and * is clocked from the main 24 MHz crystal. */ if (machine_is_davinci_dm355_evm()) { u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); phy_ctrl &= ~(3 << 9); phy_ctrl |= USBPHY_DATAPOL; __raw_writel(phy_ctrl, USB_PHY_CTRL); } /* On dm355, the default-A state machine needs DRVVBUS control. * If we won't be a host, there's no need to turn it on. */ if (cpu_is_davinci_dm355()) { u32 deepsleep = __raw_readl(DM355_DEEPSLEEP); deepsleep &= ~DRVVBUS_FORCE; __raw_writel(deepsleep, DM355_DEEPSLEEP); } /* reset the controller */ musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1); /* start the on-chip PHY and its PLL */ phy_on(); msleep(5); /* NOTE: irqs are in mixed mode, not bypass to pure-musb */ pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n", revision, __raw_readl(USB_PHY_CTRL), musb_readb(tibase, DAVINCI_USB_CTRL_REG)); musb->isr = davinci_musb_interrupt; return 0; fail: usb_put_phy(musb->xceiv); unregister: usb_nop_xceiv_unregister(); return ret; }
void musb_platform_save_context(struct musb *musb, struct musb_context_registers *musb_context) { musb_context->otg_sysconfig = musb_readl(musb->mregs, OTG_SYSCONFIG); musb_context->otg_forcestandby = musb_readl(musb->mregs, OTG_FORCESTDBY); }
int __init musb_platform_init(struct musb *musb, void *board_data) { u32 l; struct omap_musb_board_data *data = board_data; #if defined(CONFIG_ARCH_OMAP2430) omap_cfg_reg(AE5_2430_USB0HS_STP); #endif /* We require some kind of external transceiver, hooked * up through ULPI. TWL4030-family PMICs include one, * which needs a driver, drivers aren't always needed. */ musb->xceiv = otg_get_transceiver(); if (!musb->xceiv) { pr_err("HS USB OTG: no transceiver configured\n"); return -ENODEV; } musb_platform_resume(musb); l = musb_readl(musb->mregs, OTG_SYSCONFIG); l &= ~ENABLEWAKEUP; /* disable wakeup */ l &= ~NOSTDBY; /* remove possible nostdby */ l |= SMARTSTDBY; /* enable smart standby */ l &= ~AUTOIDLE; /* disable auto idle */ l &= ~NOIDLE; /* remove possible noidle */ l |= SMARTIDLE; /* enable smart idle */ /* * MUSB AUTOIDLE don't work in 3430. * Workaround by Richard Woodruff/TI */ if (!cpu_is_omap3430()) l |= AUTOIDLE; /* enable auto idle */ musb_writel(musb->mregs, OTG_SYSCONFIG, l); l = musb_readl(musb->mregs, OTG_INTERFSEL); if (data->interface_type == MUSB_INTERFACE_UTMI) { /* OMAP4 uses Internal PHY GS70 which uses UTMI interface */ l &= ~ULPI_12PIN; /* Disable ULPI */ l |= UTMI_8BIT; /* Enable UTMI */ } else { l |= ULPI_12PIN; } musb_writel(musb->mregs, OTG_INTERFSEL, l); pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, " "sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n", musb_readl(musb->mregs, OTG_REVISION), musb_readl(musb->mregs, OTG_SYSCONFIG), musb_readl(musb->mregs, OTG_SYSSTATUS), musb_readl(musb->mregs, OTG_INTERFSEL), musb_readl(musb->mregs, OTG_SIMENABLE)); if (is_host_enabled(musb)) musb->board_set_vbus = omap_set_vbus; setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); return 0; }
static int omap2430_musb_init(struct musb *musb) { u32 l; int status = 0; struct device *dev = musb->controller; struct omap2430_glue *glue = dev_get_drvdata(dev->parent); struct musb_hdrc_platform_data *plat = dev->platform_data; struct omap_musb_board_data *data = plat->board_data; /* We require some kind of external transceiver, hooked * up through ULPI. TWL4030-family PMICs include one, * which needs a driver, drivers aren't always needed. */ if (dev->parent->of_node) musb->xceiv = devm_usb_get_phy_by_phandle(dev->parent, "usb-phy", 0); else musb->xceiv = devm_usb_get_phy_dev(dev, 0); if (IS_ERR(musb->xceiv)) { status = PTR_ERR(musb->xceiv); if (status == -ENXIO) return status; pr_err("HS USB OTG: no transceiver configured\n"); return -EPROBE_DEFER; } musb->isr = omap2430_musb_interrupt; status = pm_runtime_get_sync(dev); if (status < 0) { dev_err(dev, "pm_runtime_get_sync FAILED %d\n", status); goto err1; } l = musb_readl(musb->mregs, OTG_INTERFSEL); if (data->interface_type == MUSB_INTERFACE_UTMI) { /* OMAP4 uses Internal PHY GS70 which uses UTMI interface */ l &= ~ULPI_12PIN; /* Disable ULPI */ l |= UTMI_8BIT; /* Enable UTMI */ } else { l |= ULPI_12PIN; } musb_writel(musb->mregs, OTG_INTERFSEL, l); pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, " "sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n", musb_readl(musb->mregs, OTG_REVISION), musb_readl(musb->mregs, OTG_SYSCONFIG), musb_readl(musb->mregs, OTG_SYSSTATUS), musb_readl(musb->mregs, OTG_INTERFSEL), musb_readl(musb->mregs, OTG_SIMENABLE)); setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); if (glue->status != OMAP_MUSB_UNKNOWN) omap_musb_set_mailbox(glue); usb_phy_init(musb->xceiv); pm_runtime_put_noidle(musb->controller); return 0; err1: return status; }