static void ppc7d_restart(char *cmd)
{
u32 data;
/* Disable GPP17 interrupt */
data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
data &= ~(1 << PPC7D_RST_PIN);
mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data);
/* Configure MPP17 as GPP */
data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2);
data &= ~(0x0000000f << 4);
mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data);
/* Enable pin GPP17 for output */
data = mv64x60_read(&bh, MV64x60_GPP_IO_CNTL);
data |= (1 << PPC7D_RST_PIN);
mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, data);
/* Toggle GPP9 pin to reset the board */
mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, 1 << PPC7D_RST_PIN);
mv64x60_write(&bh, MV64x60_GPP_VALUE_SET, 1 << PPC7D_RST_PIN);
for (;;) ; /* Spin until reset happens */
/* NOTREACHED */
}
/* Bridge & platform setup routines */
void __init
katana_intr_setup(void)
{
if (bh.type == MV64x60_TYPE_MV64460) /* As per instns from Marvell */
mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, 1 << 15);
/* MPP 8, 9, and 10 */
mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
/* MPP 14 */
if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I))
mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0x0f000000);
/*
* Define GPP 8,9,and 10 interrupt polarity as active low
* input signal and level triggered
*/
mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);
if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, (1<<14));
mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, (1<<14));
}
/* Config GPP intr ctlr to respond to level trigger */
mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
if (bh.type == MV64x60_TYPE_MV64360) {
/* Erratum FEr PCI-#9 */
mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD,
(1<<4) | (1<<5) | (1<<6) | (1<<7));
mv64x60_set_bits(&bh, MV64x60_PCI1_CMD, (1<<8) | (1<<9));
} else {
mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<6) | (1<<7));
mv64x60_set_bits(&bh, MV64x60_PCI1_CMD,
(1<<4) | (1<<5) | (1<<8) | (1<<9));
}
/*
* Dismiss and then enable interrupt on GPP interrupt cause
* for CPU #0
*/
mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1<<14));
mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1<<14));
}
/*
* Dismiss and then enable interrupt on CPU #0 high cause reg
* BIT25 summarizes GPP interrupts 8-15
*/
mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
}
void __init
ev64360_setup_peripherals(void)
{
u32 base;
/* Set up window for boot CS */
mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
EV64360_BOOT_WINDOW_BASE, EV64360_BOOT_WINDOW_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
/* We only use the 32-bit flash */
mv64x60_get_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, &base,
&ev64360_flash_size_0);
ev64360_flash_size_1 = 0;
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
TODC_INIT(TODC_TYPE_DS1501, 0, 0,
ioremap(EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE), 8);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
sram_base = ioremap(EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
/* Set up Enet->SRAM window */
mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
/* Give enet r/w access to memory region */
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
#if defined(CONFIG_NOT_COHERENT_CACHE)
mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
#else
mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
#endif
/*
* Setting the SRAM to 0. Note that this generates parity errors on
* internal data path in SRAM since it's first time accessing it
* while after reset it's not configured.
*/
memset(sram_base, 0, MV64360_SRAM_SIZE);
/* set up PCI interrupt controller */
ev64360_intr_setup();
}
/* Bridge & platform setup routines */
void __init
ev64360_intr_setup(void)
{
/* MPP 8, 9, and 10 */
mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
/*
* Define GPP 8,9,and 10 interrupt polarity as active low
* input signal and level triggered
*/
mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);
/* Config GPP intr ctlr to respond to level trigger */
mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
/* Erranum FEr PCI-#8 */
mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) | (1<<9));
mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) | (1<<9));
/*
* Dismiss and then enable interrupt on GPP interrupt cause
* for CPU #0
*/
mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
/*
* Dismiss and then enable interrupt on CPU #0 high cause reg
* BIT25 summarizes GPP interrupts 8-15
*/
mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
}
/* mv64360_get_irq()
*
* This function returns the lowest interrupt number of all interrupts that
* are currently asserted.
*
* Output Variable(s):
* None.
*
* Returns:
* int <interrupt number> or -2 (bogus interrupt)
*
*/
int
mv64360_get_irq(void)
{
int irq;
int irq_gpp;
#ifdef CONFIG_SMP
/*
* Second CPU gets only doorbell (message) interrupts.
* The doorbell interrupt is BIT28 in the main interrupt low cause reg.
*/
int cpu_nr = smp_processor_id();
if (cpu_nr == 1) {
if (!(mv64x60_read(&bh, MV64360_IC_MAIN_CAUSE_LO) &
(1 << MV64x60_IRQ_DOORBELL)))
return -1;
return mv64360_irq_base + MV64x60_IRQ_DOORBELL;
}
#endif
irq = mv64x60_read(&bh, MV64360_IC_MAIN_CAUSE_LO);
irq = __ilog2((irq & 0x3dfffffe) & ppc_cached_irq_mask[0]);
if (irq == -1) {
irq = mv64x60_read(&bh, MV64360_IC_MAIN_CAUSE_HI);
irq = __ilog2((irq & 0x1f0003f7) & ppc_cached_irq_mask[1]);
if (irq == -1)
irq = -2; /* bogus interrupt, should never happen */
else {
if ((irq >= 24) && (irq < MV64x60_IRQ_DOORBELL)) {
irq_gpp = mv64x60_read(&bh,
MV64x60_GPP_INTR_CAUSE);
irq_gpp = __ilog2(irq_gpp &
ppc_cached_irq_mask[2]);
if (irq_gpp == -1)
irq = -2;
else {
irq = irq_gpp + 64;
mv64x60_write(&bh,
MV64x60_GPP_INTR_CAUSE,
~(1 << (irq - 64)));
}
}
else
irq += 32;
}
}
(void)mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
if (irq < 0)
return (irq);
else
return (mv64360_irq_base + irq);
}
/* gt64260_mask_irq()
*
* This function disables the requested interrupt.
*
* Input Variable(s):
* unsigned int interrupt number (IRQ0...IRQ95).
*
* Output Variable(s):
* None.
*
* Returns:
* void
*/
static void
gt64260_mask_irq(unsigned int irq)
{
irq -= gt64260_irq_base;
if (irq > 31)
if (irq > 63) /* mask GPP irq */
mv64x60_write(&bh, MV64x60_GPP_INTR_MASK,
ppc_cached_irq_mask[2] &= ~(1 << (irq - 64)));
else /* mask high interrupt register */
mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI,
ppc_cached_irq_mask[1] &= ~(1 << (irq - 32)));
else /* mask low interrupt register */
mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO,
ppc_cached_irq_mask[0] &= ~(1 << irq));
(void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
return;
}
static irqreturn_t ppc7d_i8259_intr(int irq, void *dev_id, struct pt_regs *regs)
{
u32 temp = mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
if (temp & (1 << 28)) {
i8259_irq(regs);
mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, temp & (~(1 << 28)));
return IRQ_HANDLED;
}
return IRQ_NONE;
}
void __init ppc7d_intr_setup(void)
{
u32 data;
/*
* Define GPP 28 interrupt polarity as active high
* input signal and level triggered
*/
data = mv64x60_read(&bh, MV64x60_GPP_LEVEL_CNTL);
data &= ~(1 << 28);
mv64x60_write(&bh, MV64x60_GPP_LEVEL_CNTL, data);
data = mv64x60_read(&bh, MV64x60_GPP_IO_CNTL);
data &= ~(1 << 28);
mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, data);
/* Config GPP intr ctlr to respond to level trigger */
data = mv64x60_read(&bh, MV64x60_COMM_ARBITER_CNTL);
data |= (1 << 10);
mv64x60_write(&bh, MV64x60_COMM_ARBITER_CNTL, data);
/* XXXX Erranum FEr PCI-#8 */
data = mv64x60_read(&bh, MV64x60_PCI0_CMD);
data &= ~((1 << 5) | (1 << 9));
mv64x60_write(&bh, MV64x60_PCI0_CMD, data);
data = mv64x60_read(&bh, MV64x60_PCI1_CMD);
data &= ~((1 << 5) | (1 << 9));
mv64x60_write(&bh, MV64x60_PCI1_CMD, data);
/*
* Dismiss and then enable interrupt on GPP interrupt cause
* for CPU #0
*/
mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1 << 28));
data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
data |= (1 << 28);
mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data);
/*
* Dismiss and then enable interrupt on CPU #0 high cause reg
* BIT27 summarizes GPP interrupts 23-31
*/
mv64x60_write(&bh, MV64360_IC_MAIN_CAUSE_HI, ~(1 << 27));
data = mv64x60_read(&bh, MV64360_IC_CPU0_INTR_MASK_HI);
data |= (1 << 27);
mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI, data);
}
static irqreturn_t
mv64360_pci_error_int_handler(int irq, void *dev_id)
{
u32 val;
unsigned int pci_bus = (unsigned int)dev_id;
if (pci_bus == 0) { /* Error on PCI 0 */
val = mv64x60_read(&bh, MV64x60_PCI0_ERR_CAUSE);
printk(KERN_ERR "%s: Error in PCI %d Interface\n",
"mv64360_pci_error_int_handler", pci_bus);
printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus);
printk(KERN_ERR "\tCause register 0x%08x\n", val);
printk(KERN_ERR "\tAddress Low 0x%08x\n",
mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_LO));
printk(KERN_ERR "\tAddress High 0x%08x\n",
mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_HI));
printk(KERN_ERR "\tAttribute 0x%08x\n",
mv64x60_read(&bh, MV64x60_PCI0_ERR_DATA_LO));
printk(KERN_ERR "\tCommand 0x%08x\n",
mv64x60_read(&bh, MV64x60_PCI0_ERR_CMD));
mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, ~val);
}
if (pci_bus == 1) { /* Error on PCI 1 */
val = mv64x60_read(&bh, MV64x60_PCI1_ERR_CAUSE);
printk(KERN_ERR "%s: Error in PCI %d Interface\n",
"mv64360_pci_error_int_handler", pci_bus);
printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus);
printk(KERN_ERR "\tCause register 0x%08x\n", val);
printk(KERN_ERR "\tAddress Low 0x%08x\n",
mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_LO));
printk(KERN_ERR "\tAddress High 0x%08x\n",
mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_HI));
printk(KERN_ERR "\tAttribute 0x%08x\n",
mv64x60_read(&bh, MV64x60_PCI1_ERR_DATA_LO));
printk(KERN_ERR "\tCommand 0x%08x\n",
mv64x60_read(&bh, MV64x60_PCI1_ERR_CMD));
mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, ~val);
}
return IRQ_HANDLED;
}
static int __init
gt64260_register_hdlrs(void)
{
int rc;
/* Register CPU interface error interrupt handler */
if ((rc = request_irq(MV64x60_IRQ_CPU_ERR,
gt64260_cpu_error_int_handler, SA_INTERRUPT, CPU_INTR_STR, 0)))
printk(KERN_WARNING "Can't register cpu error handler: %d", rc);
mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0);
mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0x000000fe);
/* Register PCI 0 error interrupt handler */
if ((rc = request_irq(MV64360_IRQ_PCI0, gt64260_pci_error_int_handler,
SA_INTERRUPT, PCI0_INTR_STR, (void *)0)))
printk(KERN_WARNING "Can't register pci 0 error handler: %d",
rc);
mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0);
mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0x003c0c24);
/* Register PCI 1 error interrupt handler */
if ((rc = request_irq(MV64360_IRQ_PCI1, gt64260_pci_error_int_handler,
SA_INTERRUPT, PCI1_INTR_STR, (void *)1)))
printk(KERN_WARNING "Can't register pci 1 error handler: %d",
rc);
mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0);
mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0x003c0c24);
return 0;
}
static void ppc7d_power_off(void)
{
u32 data;
local_irq_disable();
/* Ensure that internal MV643XX watchdog is disabled.
* The Disco watchdog uses MPP17 on this hardware.
*/
data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2);
data &= ~(0x0000000f << 4);
mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data);
data = mv64x60_read(&bh, MV64x60_WDT_WDC);
if (data & 0x80000000) {
mv64x60_write(&bh, MV64x60_WDT_WDC, 1 << 24);
mv64x60_write(&bh, MV64x60_WDT_WDC, 2 << 24);
}
for (;;) ; /* No way to shut power off with software */
/* NOTREACHED */
}
/*
* gt64260_get_irq()
*
* This function returns the lowest interrupt number of all interrupts that
* are currently asserted.
*
* Input Variable(s):
* struct pt_regs* not used
*
* Output Variable(s):
* None.
*
* Returns:
* int <interrupt number> or -2 (bogus interrupt)
*/
int
gt64260_get_irq(struct pt_regs *regs)
{
int irq;
int irq_gpp;
irq = mv64x60_read(&bh, GT64260_IC_MAIN_CAUSE_LO);
irq = __ilog2((irq & 0x3dfffffe) & ppc_cached_irq_mask[0]);
if (irq == -1) {
irq = mv64x60_read(&bh, GT64260_IC_MAIN_CAUSE_HI);
irq = __ilog2((irq & 0x0f000db7) & ppc_cached_irq_mask[1]);
if (irq == -1)
irq = -2; /* bogus interrupt, should never happen */
else {
if (irq >= 24) {
irq_gpp = mv64x60_read(&bh,
MV64x60_GPP_INTR_CAUSE);
irq_gpp = __ilog2(irq_gpp &
ppc_cached_irq_mask[2]);
if (irq_gpp == -1)
irq = -2;
else {
irq = irq_gpp + 64;
mv64x60_write(&bh,
MV64x60_GPP_INTR_CAUSE,
~(1 << (irq - 64)));
}
} else
irq += 32;
}
}
(void)mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
if (irq < 0)
return (irq);
else
return (gt64260_irq_base + irq);
}
static irqreturn_t
mv64360_sram_error_int_handler(int irq, void *dev_id)
{
printk(KERN_ERR "mv64360_sram_error_int_handler: %s 0x%08x\n",
"Error in internal SRAM - Cause register",
mv64x60_read(&bh, MV64360_SRAM_ERR_CAUSE));
printk(KERN_ERR "\tSRAM error register dump:\n");
printk(KERN_ERR "\tAddress Low 0x%08x\n",
mv64x60_read(&bh, MV64360_SRAM_ERR_ADDR_LO));
printk(KERN_ERR "\tAddress High 0x%08x\n",
mv64x60_read(&bh, MV64360_SRAM_ERR_ADDR_HI));
printk(KERN_ERR "\tData Low 0x%08x\n",
mv64x60_read(&bh, MV64360_SRAM_ERR_DATA_LO));
printk(KERN_ERR "\tData High 0x%08x\n",
mv64x60_read(&bh, MV64360_SRAM_ERR_DATA_HI));
printk(KERN_ERR "\tParity 0x%08x\n",
mv64x60_read(&bh, MV64360_SRAM_ERR_PARITY));
mv64x60_write(&bh, MV64360_SRAM_ERR_CAUSE, 0);
return IRQ_HANDLED;
}
static irqreturn_t
mv64360_cpu_error_int_handler(int irq, void *dev_id)
{
printk(KERN_ERR "mv64360_cpu_error_int_handler: %s 0x%08x\n",
"Error on CPU interface - Cause regiser",
mv64x60_read(&bh, MV64x60_CPU_ERR_CAUSE));
printk(KERN_ERR "\tCPU error register dump:\n");
printk(KERN_ERR "\tAddress low 0x%08x\n",
mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_LO));
printk(KERN_ERR "\tAddress high 0x%08x\n",
mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_HI));
printk(KERN_ERR "\tData low 0x%08x\n",
mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_LO));
printk(KERN_ERR "\tData high 0x%08x\n",
mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_HI));
printk(KERN_ERR "\tParity 0x%08x\n",
mv64x60_read(&bh, MV64x60_CPU_ERR_PARITY));
mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0);
return IRQ_HANDLED;
}
void __init
katana_setup_peripherals(void)
{
u32 base;
/* Set up windows for boot CS, soldered & socketed flash, and CPLD */
mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
KATANA_BOOT_WINDOW_BASE, KATANA_BOOT_WINDOW_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
/* Assume firmware set up window sizes correctly for dev 0 & 1 */
mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, &base,
&katana_flash_size_0);
if (katana_flash_size_0 > 0) {
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
KATANA_SOLDERED_FLASH_BASE, katana_flash_size_0, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
}
mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, &base,
&katana_flash_size_1);
if (katana_flash_size_1 > 0) {
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
(KATANA_SOLDERED_FLASH_BASE + katana_flash_size_0),
katana_flash_size_1, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
}
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
KATANA_SOCKET_BASE, KATANA_SOCKETED_FLASH_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
KATANA_CPLD_BASE, KATANA_CPLD_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
cpld_base = ioremap(KATANA_CPLD_BASE, KATANA_CPLD_SIZE);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
sram_base = ioremap(KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
/* Set up Enet->SRAM window */
mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
/* Give enet r/w access to memory region */
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
/* Must wait until window set up before retrieving board id */
katana_get_board_id();
/* Enumerate pci bus (must know board id before getting proc number) */
if (katana_get_proc_num() == 0)
bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, 0);
#if defined(CONFIG_NOT_COHERENT_CACHE)
mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
#else
mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
#endif
/*
* Setting the SRAM to 0. Note that this generates parity errors on
* internal data path in SRAM since it's first time accessing it
* while after reset it's not configured.
*/
memset(sram_base, 0, MV64360_SRAM_SIZE);
/* Only processor zero [on 3750] is an PCI interrupt controller */
if (katana_get_proc_num() == 0)
katana_intr_setup();
}
static int __init
mv64360_register_hdlrs(void)
{
int rc;
/* Clear old errors and register CPU interface error intr handler */
mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0);
if ((rc = request_irq(MV64x60_IRQ_CPU_ERR + mv64360_irq_base,
mv64360_cpu_error_int_handler, IRQF_DISABLED, CPU_INTR_STR, 0)))
printk(KERN_WARNING "Can't register cpu error handler: %d", rc);
mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0);
mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0x000000ff);
/* Clear old errors and register internal SRAM error intr handler */
mv64x60_write(&bh, MV64360_SRAM_ERR_CAUSE, 0);
if ((rc = request_irq(MV64360_IRQ_SRAM_PAR_ERR + mv64360_irq_base,
mv64360_sram_error_int_handler,IRQF_DISABLED,SRAM_INTR_STR, 0)))
printk(KERN_WARNING "Can't register SRAM error handler: %d",rc);
/* Clear old errors and register PCI 0 error intr handler */
mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, 0);
if ((rc = request_irq(MV64360_IRQ_PCI0 + mv64360_irq_base,
mv64360_pci_error_int_handler,
IRQF_DISABLED, PCI0_INTR_STR, (void *)0)))
printk(KERN_WARNING "Can't register pci 0 error handler: %d",
rc);
mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0);
mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, MV64360_PCI0_ERR_MASK_VAL);
/* Erratum FEr PCI-#16 says to clear bit 0 of PCI SERRn Mask reg. */
mv64x60_write(&bh, MV64x60_PCI0_ERR_SERR_MASK,
mv64x60_read(&bh, MV64x60_PCI0_ERR_SERR_MASK) & ~0x1UL);
/* Clear old errors and register PCI 1 error intr handler */
mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, 0);
if ((rc = request_irq(MV64360_IRQ_PCI1 + mv64360_irq_base,
mv64360_pci_error_int_handler,
IRQF_DISABLED, PCI1_INTR_STR, (void *)1)))
printk(KERN_WARNING "Can't register pci 1 error handler: %d",
rc);
mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0);
mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, MV64360_PCI0_ERR_MASK_VAL);
/* Erratum FEr PCI-#16 says to clear bit 0 of PCI Intr Mask reg. */
mv64x60_write(&bh, MV64x60_PCI1_ERR_SERR_MASK,
mv64x60_read(&bh, MV64x60_PCI1_ERR_SERR_MASK) & ~0x1UL);
return 0;
}
void __init
chestnut_setup_peripherals(void)
{
mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
CHESTNUT_BOOT_8BIT_BASE, CHESTNUT_BOOT_8BIT_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
CHESTNUT_32BIT_BASE, CHESTNUT_32BIT_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
cpld_base = ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
CHESTNUT_UART_BASE, CHESTNUT_UART_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
CHESTNUT_FRAM_BASE, CHESTNUT_FRAM_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
#ifdef CONFIG_NOT_COHERENT_CACHE
mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
#else
mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
#endif
sram_base = ioremap(CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
memset(sram_base, 0, MV64360_SRAM_SIZE);
/*
* Configure MPP pins for PCI DMA
*
* PCI Slot GNT pin REQ pin
* 0 MPP16 MPP17
* 1 MPP18 MPP19
* 2 MPP20 MPP21
* 3 MPP22 MPP23
*/
mv64x60_write(&bh, MV64x60_MPP_CNTL_2,
(0x1 << 0) | /* MPPSel16 PCI0_GNT[0] */
(0x1 << 4) | /* MPPSel17 PCI0_REQ[0] */
(0x1 << 8) | /* MPPSel18 PCI0_GNT[1] */
(0x1 << 12) | /* MPPSel19 PCI0_REQ[1] */
(0x1 << 16) | /* MPPSel20 PCI0_GNT[2] */
(0x1 << 20) | /* MPPSel21 PCI0_REQ[2] */
(0x1 << 24) | /* MPPSel22 PCI0_GNT[3] */
(0x1 << 28)); /* MPPSel23 PCI0_REQ[3] */
/*
* Set unused MPP pins for output, as per schematic note
*
* Unused Pins: MPP01, MPP02, MPP04, MPP05, MPP06
* MPP09, MPP10, MPP13, MPP14, MPP15
*/
mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_0,
(0xf << 4) | /* MPPSel01 GPIO[1] */
(0xf << 8) | /* MPPSel02 GPIO[2] */
(0xf << 16) | /* MPPSel04 GPIO[4] */
(0xf << 20) | /* MPPSel05 GPIO[5] */
(0xf << 24)); /* MPPSel06 GPIO[6] */
mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1,
(0xf << 4) | /* MPPSel09 GPIO[9] */
(0xf << 8) | /* MPPSel10 GPIO[10] */
(0xf << 20) | /* MPPSel13 GPIO[13] */
(0xf << 24) | /* MPPSel14 GPIO[14] */
(0xf << 28)); /* MPPSel15 GPIO[15] */
mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL, /* Output */
BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) |
BIT(9) | BIT(10) | BIT(13) | BIT(14) | BIT(15));
/*
* Configure the following MPP pins to indicate a level
* triggered interrupt
*
* MPP24 - Board Reset (just map the MPP & GPP for chestnut_reset)
* MPP25 - UART A (high)
* MPP26 - UART B (high)
* MPP28 - PCI Slot 3 (low)
* MPP29 - PCI Slot 2 (low)
* MPP30 - PCI Slot 1 (low)
* MPP31 - PCI Slot 0 (low)
*/
mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3,
BIT(3) | BIT(2) | BIT(1) | BIT(0) | /* MPP 24 */
BIT(7) | BIT(6) | BIT(5) | BIT(4) | /* MPP 25 */
BIT(11) | BIT(10) | BIT(9) | BIT(8) | /* MPP 26 */
BIT(19) | BIT(18) | BIT(17) | BIT(16) | /* MPP 28 */
BIT(23) | BIT(22) | BIT(21) | BIT(20) | /* MPP 29 */
BIT(27) | BIT(26) | BIT(25) | BIT(24) | /* MPP 30 */
BIT(31) | BIT(30) | BIT(29) | BIT(28)); /* MPP 31 */
/*
* Define GPP 25 (high), 26 (high), 28 (low), 29 (low), 30 (low),
* 31 (low) interrupt polarity input signal and level triggered
*/
mv64x60_clr_bits(&bh, MV64x60_GPP_LEVEL_CNTL, BIT(25) | BIT(26));
mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL,
BIT(28) | BIT(29) | BIT(30) | BIT(31));
mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL,
BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
BIT(31));
/* Config GPP interrupt controller to respond to level trigger */
mv64x60_set_bits(&bh, MV64360_COMM_ARBITER_CNTL, BIT(10));
/*
* Dismiss and then enable interrupt on GPP interrupt cause for CPU #0
*/
mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE,
~(BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
BIT(31)));
mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK,
BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
BIT(31));
/*
* Dismiss and then enable interrupt on CPU #0 high cause register
* BIT27 summarizes GPP interrupts 24-31
*/
mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, BIT(27));
if (ppc_md.progress)
ppc_md.progress("chestnut_setup_bridge: exit", 0);
}
