void __init mv_init_irq(void)
{
u32 gppMask,i;
#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X)
coreId = whoAmI();
printk("IRQ initialize for core %d\n", coreId);
#endif
/* Disable all interrupts initially. */
if (0 == coreId)
{
MV_REG_WRITE(GPP_INT_MASK_REG(0), 0);
MV_REG_WRITE(GPP_INT_LVL_REG(0), 0);
}
MV_REG_WRITE(CPU_INT_MASK_LOW_REG(coreId), 0);
MV_REG_WRITE(CPU_INT_MASK_HIGH_REG(coreId), 0);
/* Set Gpp interrupts as needed */
if (0 == coreId) /*GPP for core 0 only*/
{
gppMask = mvBoardGpioIntMaskGet();
mvGppTypeSet(0, gppMask , (MV_GPP_IN & gppMask));
mvGppPolaritySet(0, gppMask , (MV_GPP_IN_INVERT & gppMask));
/* clear all int */
MV_REG_WRITE(GPP_INT_MASK_REG(0), 0);
MV_REG_WRITE(CPU_INT_MASK_HIGH_REG(coreId), IRQ_GPP_MASK);
}
else
MV_REG_WRITE(CPU_INT_MASK_HIGH_REG(coreId), 0);
/* Do the core module ones */
for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &mv_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
/* TBD. Add support for error interrupts */
return;
}
void __init mv_init_irq(void)
{
u32 gppMask,i;
/* Set Gpp interrupts as needed */
gppMask = mvBoardGpioIntMaskGet();
//jack20060626 mark
//mvGppOutEnablle(0, gppMask , (MV_GPP_IN & gppMask));
mvGppPolaritySet(0, gppMask , (MV_GPP_IN_INVERT & gppMask));
/* Disable all interrupts initially. */
MV_REG_WRITE(MV_IRQ_MASK_REG, 0x0);
MV_REG_WRITE(MV_GPP_IRQ_MASK_REG, 0x0);
/* enable GPP in the main cause */
MV_REG_BIT_SET(MV_IRQ_MASK_REG, (1 << IRQ_GPP_0_7) | (1 << IRQ_GPP_8_15));
#if defined(CONFIG_ARCH_MV88f5181)
MV_REG_BIT_SET(MV_IRQ_MASK_REG, (1 << IRQ_GPP_16_23) | (1 << IRQ_GPP_24_31));
#endif
/* clear all int */
MV_REG_WRITE(MV_IRQ_CAUSE_REG, 0x0);
MV_REG_WRITE(MV_GPP_IRQ_CAUSE_REG, 0x0);
/* Do the core module ones */
for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &mv_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
/* TBD. Add support for error interrupts */
return;
}
