/*******************************************************************************
* mvPciInit - Initialize PCI interfaces
*
* DESCRIPTION:
* This function initiate the PCI interface:
* 1) Set local bus number. In case of convential PCI it gets the bus
* number using mvPciLocalBusNumGet(). In case of PCI-X this
* information is read only.
* 2) Interface device number. In case of conventional PCI it gets the
* device number using mvPciLocalDevNumGet(). In case of PCI-X this
* information is read only.
* 3) PCI Arbiter if needed.
* 4) Enable Master and Slave on PCI interfaces.
* 5) Open PCI BARs according to default setting.
* Note that PCI bridge (P2P) is NOT initialized.
* 6) Enable CPU to PCI ordering.
*
* INPUT:
*
* pciIf - PCI interface number.
* localBus - Local Bus of the PCI interface to be set
* localDev - Local Dev of the PCI interface to be set
* bFirstCall - Indicates wether this is the first call of this
* function .
*
*
* OUTPUT:
* None.
*
* RETURN:
* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM
*
*******************************************************************************/
MV_STATUS mvPciInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod)
{
MV_PCI_BAR bar, barix;
MV_PCI_BAR_WIN dramDecWin;
MV_PCI_MODE pciMode;
MV_CPU_DEC_WIN addrDecWin;
MV_PCI_PROT_WIN pciProtWin;
MV_PCI_BAR_WIN pciBarMap[PCI_MAX_BARS];
/* Parameter checking */
if (pciIf >= mvCtrlPciMaxIfGet())
{
mvOsPrintf("mvPciInit: ERR. Invalid PCI interface %d\n", pciIf);
return MV_BAD_PARAM;
}
/* device and bus numbers */
if (MV_OK != mvPciModeGet(pciIf, &pciMode))
{
mvOsPrintf("mvPciInit: ERR. mvPciModeGet failed\n");
return MV_ERROR;
}
/* First disable all PCI target windows */
for (bar = 0; bar < PCI_MAX_BARS; bar++)
{
mvPciTargetWinEnable(pciIf, bar, MV_FALSE);
}
/* WA CQ 4382*/
MV_REG_BIT_SET(PCI_BASE_ADDR_ENABLE_REG(pciIf) ,BIT15);
/* Building in run time the pci bar mapping table */
for (bar = 0; bar < PCI_MAX_BARS; bar++)
{
for(barix = 0 ;barix < PCI_MAX_BARS; barix++)
{
if(pciBarStatusMap[barix].bar == bar)
{
pciBarMap[bar].enable = pciBarStatusMap[barix].enable;
break;
}
}
if(bar == MEM_INTER_REGS_BAR || bar == IO_INTER_REGS_BAR)
{
pciBarMap[bar].addrWin.baseLow = mvCpuIfTargetWinBaseLowGet(pciBarToTarget(bar));
pciBarMap[bar].addrWin.baseHigh = mvCpuIfTargetWinBaseHighGet(pciBarToTarget(bar));
pciBarMap[bar].addrWin.size = mvCpuIfTargetWinSizeGet(pciBarToTarget(bar));
continue;
}
if(bar == P2P_MEM0 || bar == P2P_IO)
{
pciBarMap[bar].addrWin.baseLow = 0xFFFFFFFF;
pciBarMap[bar].addrWin.baseHigh = 0;
pciBarMap[bar].addrWin.size = 0xFFFFFFFF;
continue;
}
if (mvCpuIfTargetWinGet(pciBarToTarget(bar), &addrDecWin) == MV_OK)
{
pciBarMap[bar].addrWin.baseLow = addrDecWin.addrWin.baseLow;
pciBarMap[bar].addrWin.baseHigh = addrDecWin.addrWin.baseHigh;
pciBarMap[bar].addrWin.size = addrDecWin.addrWin.size;
if(addrDecWin.enable == MV_FALSE)
{
pciBarMap[bar].enable = DIS;
}
}
else
{
pciBarMap[bar].addrWin.baseLow = 0xFFFFFFFF;
pciBarMap[bar].addrWin.baseHigh = 0;
pciBarMap[bar].addrWin.size = 0xFFFFFFFF;
pciBarMap[bar].enable = DIS;
}
}
/* finally fill table with TBL_TERM entry */
bar = PCI_MAX_BARS - 1;
pciBarMap[bar].addrWin.baseLow = TBL_TERM;
pciBarMap[bar].addrWin.baseHigh = TBL_TERM;
pciBarMap[bar].addrWin.size = TBL_TERM;
pciBarMap[bar].enable = TBL_TERM;
/* Memory Mapped Internal Registers BAR can not be disabled. */
/* Relocate its BAR first to avoid colisions with other BARs (e.g DRAM) */
if (MV_OK != mvPciTargetWinSet(pciIf, MEM_INTER_REGS_BAR,
&pciBarMap[MEM_INTER_REGS_BAR]))
{
mvOsPrintf("mvPciInit: ERR. mvPciTargetWinSet failed\n");
return MV_ERROR;
}
/* Now, go through all targets in default table until table terminator */
for (bar = 0; pciBarMap[bar].enable != TBL_TERM; bar++)
{
/* Skip the P2P BARs. They should be configured seperately */
if (0xFFFFFFFF == pciBarMap[bar].addrWin.baseLow)
{
continue;
}
/* check if the size passed is zero ! */
if (0 == pciBarMap[bar].addrWin.size)
{
/* disable the bar */
mvPciTargetWinEnable(pciIf,bar,MV_FALSE);
continue;
}
/* Get DRAM parameters from CPU interface */
if (MV_PCI_BAR_IS_DRAM_BAR(bar))
{
if (MV_OK != mvCpuIfTargetWinGet(MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar),
&addrDecWin))
{
mvOsPrintf("mvPciInit:ERR. targetWinGet %d fail\n", bar);
return MV_ERROR;
}
dramDecWin.addrWin.baseLow = addrDecWin.addrWin.baseLow;
dramDecWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh;
dramDecWin.addrWin.size = addrDecWin.addrWin.size;
dramDecWin.enable = addrDecWin.enable;
if (MV_OK != mvPciTargetWinSet(pciIf, bar, &dramDecWin))
{
mvOsPrintf("mvPciInit: ERR. mvPciTargetWinSet %d failed\n",bar);
return MV_ERROR;
}
continue;
}
if (MV_OK != mvPciTargetWinSet(pciIf, bar, &pciBarMap[bar]))
{
mvOsPrintf("mvPciInit: ERR. mvPciTargetWinSet %d failed\n", bar);
return MV_ERROR;
}
}
MV_REG_BIT_SET(PCI_ADDR_DECODE_CONTROL_REG(pciIf),
PADCR_REMAP_REG_WR_DIS);
/* configure access control unit 0 to DDR to enhance performance */
pciProtWin.addrWin.baseLow = 0;
pciProtWin.addrWin.baseHigh = 0;
pciProtWin.addrWin.size = mvDramIfSizeGet();
pciProtWin.attributes.access = ALLOWED;
pciProtWin.attributes.write = ALLOWED;
pciProtWin.attributes.swapType = MV_BYTE_SWAP;
pciProtWin.attributes.readMaxBurst = 128;
pciProtWin.attributes.readBurst = 256;
pciProtWin.attributes.writeMaxBurst = 128;
pciProtWin.attributes.pciOrder = MV_FALSE;
pciProtWin.enable = MV_TRUE;
if( mvPciProtWinSet(pciIf, 0, &pciProtWin) != MV_OK )
{
mvOsPrintf("mvPciInit: ERR. mvPciProtWinSet failed\n");
return MV_ERROR;
}
mvPciHalInit(pciIf, pciIfmod);
return MV_OK;
}
/* u-boot interface function to SDRAM init - this is where all the
* controlling logic happens */
long int initdram(int board_type)
{
MV_VOIDFUNCPTR pRom;
MV_U32 forcedCl; /* Forced CAS Latency */
MV_U32 totalSize;
char * env;
MV_TWSI_ADDR slave;
/* r0 <- current position of code */
/* test if we run from flash or RAM */
if(dramBoot != 1)
{
slave.type = ADDR7_BIT;
slave.address = 0;
mvTwsiInit(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_TCLK, &slave, 0);
/* Calculating MIN/MAX CAS latency according to user settings */
env = getenv("CASset");
if(env && (strcmp(env,"1.5") == 0))
{
forcedCl = 15;
}
else if(env && (strcmp(env,"2") == 0))
{
forcedCl = 20;
}
else if(env && (strcmp(env,"2.5") == 0))
{
forcedCl = 25;
}
else if(env && (strcmp(env,"3") == 0))
{
forcedCl = 30;
}
else if(env && (strcmp(env,"4") == 0))
{
forcedCl = 40;
}
else if(env && (strcmp(env,"5") == 0))
{
forcedCl = 50;
}
else if(env && (strcmp(env,"6") == 0))
{
forcedCl = 60;
}
else
{
forcedCl = 0;
}
/* detect the dram configuartion parameters */
if (MV_OK != mvDramIfDetect(forcedCl,1))
{
printf("DRAM Auto Detection Failed! System Halt!\n");
return 0;
}
/* set the dram configuration */
/* Calculate jump address of _mvDramIfConfig() */
#if defined(MV_BOOTROM)
pRom = (MV_VOIDFUNCPTR)(((MV_VOIDFUNCPTR)_mvDramIfConfig - (MV_VOIDFUNCPTR)_start) +
(MV_VOIDFUNCPTR)CONFIG_SYS_MONITOR_BASE + (MV_VOIDFUNCPTR)MONITOR_HEADER_LEN);
#else
pRom = (MV_VOIDFUNCPTR)(((MV_VOIDFUNCPTR)_mvDramIfConfig - (MV_VOIDFUNCPTR)_start) +
(MV_VOIDFUNCPTR)CONFIG_SYS_MONITOR_BASE);
#endif
(*pRom) (); /* Jump to _mvDramIfConfig*/
}
totalSize = mvDramIfSizeGet();
return(totalSize);
}
