MV_VOID mvEth1121PhyBasicInit(MV_U32 port)
{
MV_U16 value;
MV_U16 phyAddr = mvBoardPhyAddrGet(port);
MV_REG_WRITE(ETH_PHY_ADDR_REG(port), phyAddr);
/* Change page select to 2 */
value = 2;
mvEthPhyRegWrite(phyAddr, 22, value);
mvOsDelay(10);
/* Set RGMII rx delay */
mvEthPhyRegRead(phyAddr, 21, &value);
value |= BIT5;
mvEthPhyRegWrite(phyAddr, 21, value);
mvOsDelay(10);
/* Change page select to 0 */
value = 0;
mvEthPhyRegWrite(phyAddr, 22, value);
mvOsDelay(10);
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, &value);
value |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, value);
mvOsDelay(10);
}
void mvEthSwitchRegWrite(MV_U32 ethPortNum, MV_U32 phyAddr,
MV_U32 regOffs, MV_U16 data)
{
MV_U16 reg;
if(switchMultiChipMode == 0xdeadbeef) {
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum) ,0x2, ®);
if(reg == 0xffff)
switchMultiChipMode = mvBoardPhyAddrGet(ethPortNum);
else
switchMultiChipMode = 0xffffffff;
}
if(switchMultiChipMode == 0xffffffff)
mvEthPhyRegWrite(phyAddr, regOffs, data);
else //If Switch is in multichip mode, need to use indirect register access
{
do {
mvEthPhyRegRead(switchMultiChipMode, 0x0, ®);
} while((reg & BIT15)); // Poll till SMIBusy bit is clear
mvEthPhyRegWrite(switchMultiChipMode, 0x1, data); // Write data to Switch indirect data register
mvEthPhyRegWrite(switchMultiChipMode, 0x0, regOffs | (phyAddr << 5) |
BIT10 | BIT12 | BIT15); // Write command to Switch indirect command register
}
}
MV_VOID mvEth1121PhyBasicInit(MV_U32 phyAddr)
{
MV_U16 value;
/* Change page select to 2 */
value = 2;
mvEthPhyRegWrite(phyAddr, 22, value);
mvOsDelay(10);
/* Set RGMII rx delay */
mvEthPhyRegRead(phyAddr, 21, &value);
value |= BIT5;
mvEthPhyRegWrite(phyAddr, 21, value);
mvOsDelay(10);
/* Change page select to 0 */
value = 0;
mvEthPhyRegWrite(phyAddr, 22, value);
mvOsDelay(10);
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, &value);
value |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, value);
mvOsDelay(10);
}
MV_VOID mvEth1340PhyBasicInit(void)
{
int i;
MV_U16 reg;
int startAddr, endAddr;
startAddr = ethphyHalData.quadPhyStartAddr;
endAddr = startAddr + 4;
for (i = startAddr; i < endAddr; i++) {
mvEthPhyRegWrite(i, 0x16, 0);
mvEthPhyRegWrite(i, 0x1d, 3);
mvEthPhyRegWrite(i, 0x1e, 2);
mvEthPhyRegWrite(i, 0x1d, 0);
/* Power up the phy */
/* mvEthPhyRegRead(i,ETH_PHY_CTRL_REG, ®); */
/* reg |= ETH_PHY_CTRL_RESET_MASK; */
/* mvEthPhyRegWrite(i,ETH_PHY_CTRL_REG, reg); software reset */
/* Enable QSGMII AN */
/* Set page to 4. */
mvEthPhyRegWrite(i, 0x16, 4);
/* Enable AN */
mvEthPhyRegWrite(i, 0x0, 0x1140);
/* Set page to 0. */
mvEthPhyRegWrite(i, 0x16, 0);
mvEthPhyRegRead(i, ETH_PHY_CTRL_REG, ®);
reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
mvEthPhyRegWrite(i, ETH_PHY_CTRL_REG, reg);
}
}
/******************************************************************************
* mv_eth_tool_write_phy_reg
* Description:
* Marvell PHY register write (includes page number)
* INPUT:
* phy_addr PHY address
* page PHY register page (region)
* reg PHY register number (offset)
* data Data to be written into PHY register
* OUTPUT
* None
* RETURN:
* 0 for success
*
*******************************************************************************/
int mv_eth_tool_write_phy_reg(int phy_addr, u16 page, u16 reg, u16 data)
{
unsigned long flags;
MV_STATUS status = 0;
spin_lock_irqsave(&mii_lock, flags);
/* setup register address page first */
if (!mvEthPhyRegWrite(phy_addr, MV_ETH_TOOL_PHY_PAGE_ADDR_REG,
(unsigned int)page)) {
status = mvEthPhyRegWrite(phy_addr, reg, data);
}
spin_unlock_irqrestore(&mii_lock, flags);
return status;
}
/*******************************************************************************
* mvEthE1310PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* ethPortNum - Ethernet port number
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE1310PhyBasicInit(MV_U32 ethPortNum)
{
MV_U16 reg;
/* Set phy address */
MV_REG_WRITE(ETH_PHY_ADDR_REG(ethPortNum), mvBoardPhyAddrGet(ethPortNum));
/* Leds link and activity*/
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x3);
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),16,®);
reg &= ~0xf;
reg |= 0x11;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,reg);
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x0);
}
/*******************************************************************************
* mvEthPhyRestartAN - Restart ethernet Phy Auto-Negotiation.
*
* DESCRIPTION:
* This function resets a given ethernet Phy.
*
* INPUT:
* phyAddr - Phy address.
* timeout - in millisec; 0 - no timeout (don't wait)
*
* OUTPUT:
* None.
*
* RETURN: MV_OK - Success
* MV_TIMEOUT - Timeout
*
*******************************************************************************/
MV_STATUS mvEthPhyRestartAN(MV_U32 phyAddr, int timeout)
{
MV_U16 phyRegData;
/* Reset the PHY */
if (mvEthPhyRegRead(phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK)
return MV_FAIL;
/* Set bit 12 to Enable autonegotiation of the PHY */
phyRegData |= ETH_PHY_CTRL_AN_ENABLE_MASK;
/* Set bit 9 to Restart autonegotiation of the PHY */
phyRegData |= ETH_PHY_CTRL_AN_RESTART_MASK;
mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, phyRegData);
if (timeout == 0)
return MV_OK;
/* Wait untill Auotonegotiation completed */
while (timeout > 0) {
mvOsSleep(100);
timeout -= 100;
if (mvEthPhyRegRead(phyAddr, ETH_PHY_STATUS_REG, &phyRegData) != MV_OK)
return MV_FAIL;
if (phyRegData & ETH_PHY_STATUS_AN_DONE_MASK)
return MV_OK;
}
return MV_TIMEOUT;
}
/*******************************************************************************
* mvEthPhyReset - Reset ethernet Phy.
*
* DESCRIPTION:
* This function resets a given ethernet Phy.
*
* INPUT:
* phyAddr - Phy address.
* timeout - in millisec
*
* OUTPUT:
* None.
*
* RETURN: MV_OK - Success
* MV_TIMEOUT - Timeout
*
*******************************************************************************/
MV_STATUS mvEthPhyReset(MV_U32 phyAddr, int timeout)
{
MV_U16 phyRegData;
/* Reset the PHY */
if (mvEthPhyRegRead(phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK)
return MV_FAIL;
/* Set bit 15 to reset the PHY */
phyRegData |= ETH_PHY_CTRL_RESET_MASK;
mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, phyRegData);
/* Wait untill Reset completed */
while (timeout > 0) {
mvOsSleep(100);
timeout -= 100;
if (mvEthPhyRegRead(phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK)
return MV_FAIL;
if ((phyRegData & ETH_PHY_CTRL_RESET_MASK) == 0)
return MV_OK;
}
return MV_TIMEOUT;
}
/*******************************************************************************
* mvEthSgmiiToCopperPhyInit - Initialize Test board 1112 Phy
*
* DESCRIPTION:
*
* INPUT:
* phyAddr - Phy address.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvEthSgmiiToCopperPhyBasicInit(MV_U32 port)
{
MV_U16 value;
MV_U16 phyAddr = 0xC;
/* Port 0 phyAdd c */
/* Port 1 phyAdd d */
mvEthPhyRegWrite(phyAddr + port, 22, 3);
mvEthPhyRegWrite(phyAddr + port, 16, 0x103);
mvEthPhyRegWrite(phyAddr + port, 22, 0);
/* reset the phy */
mvEthPhyRegRead(phyAddr + port, 0, &value);
value |= BIT15;
mvEthPhyRegWrite(phyAddr + port, 0, value);
}
/*******************************************************************************
* mvEthE1111PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* ethPortNum - Ethernet port number
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE1111PhyBasicInit(MV_U32 ethPortNum)
{
MV_U16 reg;
/* Phy recv and tx delay */
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),20,®);
reg |= BIT1 | BIT7;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),20,reg);
/* Leds link and activity*/
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),24,0x4111);
/* reset the phy */
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0,®);
reg |= BIT15;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg);
}
/*******************************************************************************
* mvEthE1116PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* ethPortNum - Ethernet port number
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE1116PhyBasicInit(MV_U32 ethPortNum)
{
MV_U16 reg;
/* Set phy address */
MV_REG_WRITE(ETH_PHY_ADDR_REG(ethPortNum), mvBoardPhyAddrGet(ethPortNum));
/* Leds link and activity*/
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x3);
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),16,®);
reg &= ~0xf;
reg |= 0x1;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,reg);
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x0);
/* Set RGMII delay */
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,2);
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),21,®);
reg |= (BIT5 | BIT4);
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),21,reg);
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0);
/* reset the phy */
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0,®);
reg |= BIT15;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg);
}
/*******************************************************************************
* mvEthE1011PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* phyAddr - PHY address.
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE1011PhyBasicInit(MV_U32 phyAddr)
{
MV_U16 reg;
/* Phy recv and tx delay */
mvEthPhyRegRead(phyAddr, 20, ®);
reg &= ~(BIT1 | BIT7);
mvEthPhyRegWrite(phyAddr, 20, reg);
/* Leds link and activity*/
mvEthPhyRegWrite(phyAddr, 24, 0x4111);
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, ®);
reg |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, reg);
}
/******************************************************************************
* mv_eth_tool_write_mdio
* Description:
* MDIO write implementation for kernel core MII calls
* INPUT:
* netdev Network device structure pointer
* addr PHY address
* reg PHY register number (offset)
* data Data to be written into PHY register
* OUTPUT
* None
*
*******************************************************************************/
void mv_eth_tool_write_mdio(struct net_device *netdev, int addr, int reg, int data)
{
unsigned long flags;
unsigned short tmp = (unsigned short)data;
spin_lock_irqsave(&mii_lock, flags);
mvEthPhyRegWrite(addr, reg, tmp);
spin_unlock_irqrestore(&mii_lock, flags);
}
MV_VOID mvEth1540PhyBasicInit(MV_BOOL eeeEnable)
{
MV_U16 reg;
int startAddr;
startAddr = ethphyHalData.quadPhyStartAddr;
/* Identify PHY Revision. */
mvEthPhyRegWrite(startAddr, 0x16, 0xFB);
mvEthPhyRegRead(startAddr, 0x1F, ®);
mvEthPhyRegWrite(startAddr, 0x16, 0x0);
if (reg == 0x100)
mvEth1540Y0PhyBasicInit(eeeEnable);
else
mvEth1540A0PhyBasicInit(eeeEnable);
return;
}
/*******************************************************************************
* mvEthE3016PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* phyAddr - PHY address.
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE3016PhyBasicInit(MV_U32 phyAddr)
{
MV_U16 reg;
/* Leds link and activity*/
mvEthPhyRegRead(phyAddr, 22, ®);
reg &= ~0xf;
reg |= 0xa;
mvEthPhyRegWrite(phyAddr, 22, reg);
/* Set RGMII (RX) delay and copper mode */
mvEthPhyRegRead(phyAddr, 28, ®);
reg &= ~(BIT3 | BIT10 | BIT11);
reg |= (BIT10);
mvEthPhyRegWrite(phyAddr, 28, reg);
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, ®);
reg |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, reg);
}
/*******************************************************************************
* mvEthE6131PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* ethPortNum - Ethernet port number
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE6131SwitchBasicInit(MV_U32 ethPortNum)
{
MV_U16 reg;
/*Enable Phy power up*/
mvEthPhyRegWrite (0,0,0x9140);
mvEthPhyRegWrite (1,0,0x9140);
mvEthPhyRegWrite (2,0,0x9140);
/*Enable PPU*/
mvEthPhyRegWrite (0x1b,4,0x4080);
/*Enable Phy detection*/
mvEthPhyRegRead (0x13,0,®);
reg &= ~(1<<12);
mvEthPhyRegWrite (0x13,0,reg);
mvOsDelay(100);
mvEthPhyRegWrite (0x13,1,0x33);
switchVlanInit(ethPortNum,
MV_E6131_CPU_PORT,
MV_E6131_MAX_PORTS_NUM,
MV_E6131_PORTS_OFFSET,
MV_E6131_ENABLED_PORTS);
}
/*******************************************************************************
* mvEthE1111PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* phyAddr - PHY address.
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE1111PhyBasicInit(MV_U32 phyAddr)
{
MV_U16 reg;
/* Phy recv and tx delay */
mvEthPhyRegRead(phyAddr, 20, ®);
reg |= BIT1 | BIT7;
mvEthPhyRegWrite(phyAddr, 20, reg);
/* Leds link and activity*/
mvEthPhyRegWrite(phyAddr, 24, 0x4111);
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, ®);
reg |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, reg);
if (ethphyHalData.boardSpecInit == MV_TRUE)
mvEthPhyRegWrite(phyAddr,
ethphyHalData.specRegOff , ethphyHalData.specData);
}
/*******************************************************************************
* mvEthPhyDisableAN - Disable Phy Auto-Negotiation and set forced Speed and Duplex
*
* DESCRIPTION:
* This function disable AN and set duplex and speed.
*
* INPUT:
* phyAddr - Phy address.
* speed - port speed. 0 - 10 Mbps, 1-100 Mbps, 2 - 1000 Mbps
* duplex - port duplex. 0 - Half duplex, 1 - Full duplex
*
* OUTPUT:
* None.
*
* RETURN: MV_OK - Success
* MV_FAIL - Failure
*
*******************************************************************************/
MV_STATUS mvEthPhyDisableAN(MV_U32 phyAddr, int speed, int duplex)
{
MV_U16 phyRegData;
if(mvEthPhyRegRead (phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK)
return MV_FAIL;
switch(speed)
{
case 0: /* 10 Mbps */
phyRegData &= ~ETH_PHY_CTRL_SPEED_LSB_MASK;
phyRegData &= ~ETH_PHY_CTRL_SPEED_MSB_MASK;
break;
case 1: /* 100 Mbps */
phyRegData |= ETH_PHY_CTRL_SPEED_LSB_MASK;
phyRegData &= ~ETH_PHY_CTRL_SPEED_MSB_MASK;
break;
case 2: /* 1000 Mbps */
phyRegData &= ~ETH_PHY_CTRL_SPEED_LSB_MASK;
phyRegData |= ETH_PHY_CTRL_SPEED_MSB_MASK;
break;
default:
mvOsOutput("Unexpected speed = %d\n", speed);
return MV_FAIL;
}
switch(duplex)
{
case 0: /* half duplex */
phyRegData &= ~ETH_PHY_CTRL_DUPLEX_MASK;
break;
case 1: /* full duplex */
phyRegData |= ETH_PHY_CTRL_DUPLEX_MASK;
break;
default:
mvOsOutput("Unexpected duplex = %d\n", duplex);
}
/* Clear bit 12 to Disable autonegotiation of the PHY */
phyRegData &= ~ETH_PHY_CTRL_AN_ENABLE_MASK;
/* Clear bit 9 to DISABLE, Restart autonegotiation of the PHY */
phyRegData &= ~ETH_PHY_CTRL_AN_RESTART_MASK;
mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, phyRegData);
return MV_OK;
}
/*******************************************************************************
* mvEth1145PhyInit - Initialize MARVELL 1145 Phy
*
* DESCRIPTION:
*
* INPUT:
* phyAddr - Phy address.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvEth1145PhyBasicInit(MV_U32 phyAddr)
{
MV_U16 value;
/* Set Link1000 output pin to be link indication, set Tx output pin to be activity */
mvEthPhyRegWrite(phyAddr, 0x18, ETH_PHY_LED_ACT_LNK_DV);
mvOsDelay(10);
/* Add delay to RGMII Tx and Rx */
mvEthPhyRegRead(phyAddr, 0x14, &value);
mvEthPhyRegWrite(phyAddr, 0x14, (value | BIT1 | BIT7));
mvOsDelay(10);
/* Set Phy TPVL to 0 */
mvEthPhyRegWrite(phyAddr, 0x10, 0x60);
mvOsDelay(10);
/* Reset Phy */
mvEthPhyRegRead(phyAddr, 0x00, &value);
mvEthPhyRegWrite(phyAddr, 0x00, (value | BIT15));
mvOsDelay(10);
return;
}
/*******************************************************************************
* mvEthE3016PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* ethPortNum - Ethernet port number
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE3016PhyBasicInit(MV_U32 ethPortNum)
{
MV_U16 reg;
/* Set phy address */
MV_REG_WRITE(ETH_PHY_ADDR_REG(ethPortNum), mvBoardPhyAddrGet(ethPortNum));
/* Leds link and activity*/
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),22,®);
reg &= ~0xf;
reg |= 0xa;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,reg);
/* Set RGMII (RX) delay and copper mode */
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),28,®);
reg &= ~(BIT3 | BIT10 | BIT11);
reg |= (BIT10);
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),28,reg);
/* reset the phy */
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0,®);
reg |= BIT15;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg);
}
static GT_BOOL mv_switch_mii_write(GT_QD_DEV *dev, unsigned int phy, unsigned int reg, unsigned int data)
{
unsigned long flags;
unsigned short tmp;
MV_STATUS status;
spin_lock_irqsave(&switch_lock, flags);
tmp = (unsigned short)data;
status = mvEthPhyRegWrite(phy, reg, tmp);
spin_unlock_irqrestore(&switch_lock, flags);
if (status == MV_OK)
return GT_TRUE;
return GT_FALSE;
}
GT_BOOL writeMiiWrap(GT_QD_DEV* dev, unsigned int portNumber, unsigned int MIIReg, unsigned int data)
{
unsigned long flags;
unsigned short tmp;
MV_STATUS status;
spin_lock_irqsave(&switch_lock, flags);
tmp = (unsigned short)data;
status = mvEthPhyRegWrite(portNumber, MIIReg, tmp);
spin_unlock_irqrestore(&switch_lock, flags);
if (status == MV_OK)
return GT_TRUE;
return GT_FALSE;
}
MV_VOID mvEthInternalGEPhyBasicInit(MV_U32 phyAddr)
{
MV_U16 value;
if (ethphyHalData.ctrlRevId < 2) {
mvEthPhyRegWrite(phyAddr, 0x16, 0x00FF);
mvEthPhyRegWrite(phyAddr, 0x11, 0x0FD0);
mvEthPhyRegWrite(phyAddr, 0x10, 0x214C);
mvEthPhyRegWrite(phyAddr, 0x11, 0x0000);
mvEthPhyRegWrite(phyAddr, 0x10, 0x2000);
mvEthPhyRegWrite(phyAddr, 0x11, 0x0F16);
mvEthPhyRegWrite(phyAddr, 0x10, 0x2146);
mvEthPhyRegWrite(phyAddr, 0x16, 0x0);
}
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, &value);
value |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, value);
mvOsDelay(10);
return;
}
/*******************************************************************************
* mvEthE1112PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* phyAddr - PHY address.
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE1112PhyBasicInit(MV_U32 phyAddr)
{
MV_U16 reg;
/* Set phy address */
/*MV_REG_WRITE(ETH_PHY_ADDR_REG(ethPortNum), mvBoardPhyAddrGet(ethPortNum));*/
/* Implement PHY errata */
mvEthPhyRegWrite(phyAddr, 22, 2);
mvEthPhyRegWrite(phyAddr, 0, 0x140);
mvEthPhyRegWrite(phyAddr, 0, 0x8140);
mvEthPhyRegWrite(phyAddr, 22, 0);
mvEthPhyRegWrite(phyAddr, 22, 3);
mvEthPhyRegWrite(phyAddr, 16, 0x103);
mvEthPhyRegWrite(phyAddr, 22, 0);
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, ®);
reg |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, reg);
}
int mv_eth_write_mii(unsigned int portNumber, unsigned int MIIReg, unsigned int data)
{
unsigned long flags;
unsigned short tmp;
MV_STATUS status;
spin_lock_irqsave(&mii_lock, flags);
tmp = (unsigned short)data;
#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X)
mvSemaLock(MV_SEMA_SMI);
#endif
status = mvEthPhyRegWrite(mvBoardPhyAddrGet(portNumber), MIIReg, tmp);
#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X)
mvSemaUnlock(MV_SEMA_SMI);
#endif
spin_unlock_irqrestore(&mii_lock, flags);
if (status == MV_OK)
return 0;
return -1;
}
/*******************************************************************************
* mvEthE1116PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* phyAddr - PHY address.
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE1116PhyBasicInit(MV_U32 phyAddr)
{
MV_U16 reg;
/* Leds link and activity*/
mvEthPhyRegWrite(phyAddr, 22, 0x3);
mvEthPhyRegRead(phyAddr, 16, ®);
reg &= ~0xf;
reg |= 0x1;
mvEthPhyRegWrite(phyAddr, 16, reg);
mvEthPhyRegWrite(phyAddr, 22, 0x0);
/* Set RGMII delay */
mvEthPhyRegWrite(phyAddr, 22, 2);
mvEthPhyRegRead(phyAddr, 21, ®);
reg |= (BIT5 | BIT4);
mvEthPhyRegWrite(phyAddr, 21, reg);
mvEthPhyRegWrite(phyAddr, 22, 0);
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, ®);
reg |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, reg);
}
int evb_resource_dump_write(struct file *file, const char *buffer, unsigned long count, void *data)
{
/* Reading / Writing from system controller internal registers */
if (!strncmp(buffer, "register", 8)) {
if (buffer[10] == 'r') {
evb_resource_dump_request = atoh((char *)((unsigned int)buffer + 12), 8);
evb_resource_dump_result = MV_REG_READ(evb_resource_dump_request);
}
if (buffer[10] == 'w') {
evb_resource_dump_request = atoh((char *)((unsigned int)buffer + 12), 8);
evb_resource_dump_result = atoh((char *)((unsigned int)buffer + 12 + 8 + 1), 8);
MV_REG_WRITE(evb_resource_dump_request, evb_resource_dump_result);
}
}
/* Reading / Writing from 32bit address - mostly usable for memory */
if (!strncmp(buffer, "memory ", 8)) {
if (buffer[10] == 'r') {
evb_resource_dump_request = atoh((char *)((unsigned int)buffer + 12), 8);
evb_resource_dump_result = *(unsigned int *)evb_resource_dump_request;
}
if (buffer[10] == 'w') {
evb_resource_dump_request = atoh((char *)((unsigned int)buffer + 12), 8);
evb_resource_dump_result = atoh((char *)((unsigned int)buffer + 12 + 8 + 1), 8);
*(unsigned int *)evb_resource_dump_request = evb_resource_dump_result;
}
}
/* Reading / Writing from a rgister via SMI */
if (!strncmp(buffer, "smi", 3)) {
unsigned short regVal;
unsigned int dev_addr = atoh((char *)((unsigned int)buffer + 7), 8);
if (buffer[5] == 'r') {
evb_resource_dump_request = atoh((char *)((unsigned int)buffer + 7 + 8 + 1), 8);
regVal = 0;
mvEthPhyRegRead(dev_addr, evb_resource_dump_request, ®Val);
evb_resource_dump_result = (u32) regVal;
}
if (buffer[5] == 'w') {
evb_resource_dump_request = atoh((char *)((unsigned int)buffer + 7 + 8 + 1), 8);
evb_resource_dump_result = atoh((char *)((unsigned int)buffer + 7 + 8 + 8 + 2), 8);
mvEthPhyRegWrite(dev_addr, evb_resource_dump_request, (u16) evb_resource_dump_result);
}
}
#ifdef CONFIG_MV_CPU_PERF_CNTRS
if (!strncmp(buffer, "start_cc", 8)) {
int cc0, cc1, cc2, cc3;
sscanf((char *)((unsigned int)buffer + 8), "%d %d %d %d", &cc0, &cc1, &cc2, &cc3);
mv_proc_start_cntrs(cc0, cc1, cc2, cc3);
}
if (!strncmp(buffer, "show__cc", 8))
mv_proc_show_cntrs();
#endif /* */
#ifdef CONFIG_MV_CPU_L2_PERF_CNTRS
if (!strncmp(buffer, "start_l2", 8)) {
int l20, l21;
sscanf((char *)((unsigned int)buffer + 8), "%d %d", &l20, &l21);
mv_proc_start_l2_cntrs(l20, l21);
}
if (!strncmp(buffer, "show__l2", 8))
mv_proc_show_l2_cntrs();
#endif /* */
#ifdef CONFIG_MV_DRAM_STATS_CNTRS
if (!strncmp(buffer, "start_dram_stats", strlen("start_dram_stats"))) {
int mode0, mode1;
sscanf((char *)((unsigned int)buffer + strlen("start_dram_stats")), "%d %d", &mode0, &mode1);
mv_proc_start_dram_stats_cntrs(mode0, mode1);
}
if (!strncmp(buffer, "stop_dram_stats", strlen("stop_dram_stats")))
mvDramStatStop();
if (!strncmp(buffer, "show_dram_stats", strlen("show_dram_stats")))
mv_proc_show_dram_stats_cntrs();
#endif /* */
if (!strncmp(buffer, "idle_wfi", strlen("idle_wfi"))) {
int en;
sscanf((char *)((unsigned int)buffer + strlen("idle_wfi")), "%d", &en);
support_wait_for_interrupt = en;
}
if (!strncmp(buffer, "show__ua", 8)) {
if (kernel_align == 1)
kernel_align = 0;
else
kernel_align = 1;
printk(KERN_INFO "debug kernel align %d\n", kernel_align);
}
if (!strncmp(buffer, "cpu_freq", strlen("cpu_freq"))) {
buffer += strlen("cpu_freq") + 1;
if (!strncmp(buffer, "normal", strlen("normal"))) {
printk(KERN_INFO "Entering fast mode.\n");
mvCtrlPwrSaveOff();
} else if (!strncmp(buffer, "ddr", strlen("ddr"))) {
printk(KERN_INFO "Entering slow mode.\n");
mvCtrlPwrSaveOn();
}
}
#if 0
if (!strncmp(buffer, "ddd", 3)) {
unsigned int ii[10];
int ip, sum = 0;
volatile unsigned int *tt = (unsigned int *)((unsigned int)ii + 2);
MV_CPU_CNTRS_EVENT *hal_rx_event = NULL;
/* 0 - instruction counters */
mvCpuCntrsProgram(0, MV_CPU_CNTRS_INSTRUCTIONS, "Instr", 25);
/* 1 - ICache misses counter */
mvCpuCntrsProgram(1, MV_CPU_CNTRS_ICACHE_READ_MISS, "IcMiss", 0);
/* 2 - cycles counter */
mvCpuCntrsProgram(2, MV_CPU_CNTRS_CYCLES, "Cycles", 21);
/* 3 - DCache read misses counter */
mvCpuCntrsProgram(3, MV_CPU_CNTRS_DCACHE_READ_MISS, "DcRdMiss", 0);
hal_rx_event = mvCpuCntrsEventCreate("HAL_RX", 1);
MV_CPU_CNTRS_START(hal_rx_event);
for (ip = 0; ip < 1000; ip++)
sum += *tt;
MV_CPU_CNTRS_STOP(hal_rx_event);
MV_CPU_CNTRS_SHOW(hal_rx_event);
}
#endif /* */
return count;
}
void kw_wol_configure(void)
{
MV_U16 phyAddr = mvBoardPhyAddrGet(WOL_PORT_NUM);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x16, 0x3);
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x12, 0x4905);
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x10, 0x181B);
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x16, 0x0);
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x0, 0x8000);
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x12, 0x80);
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x16, 0x11);
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x17, ((mvMacAddr[WOL_PORT_NUM][5] << 8) | (mvMacAddr[WOL_PORT_NUM][4])));
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x18, ((mvMacAddr[WOL_PORT_NUM][3] << 8) | (mvMacAddr[WOL_PORT_NUM][2])));
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x19, ((mvMacAddr[WOL_PORT_NUM][1] << 8) | (mvMacAddr[WOL_PORT_NUM][0])));
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x10, 0x4500);
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x16, 0x3);
mvOsDelay(10);
/* configure SMI (system management interrupt) register */
MV_MEMIO_LE32_WRITE(MV_SYS_MANAG_INTERRUPT_REG, 0x02404185);
mvOsDelay(10);
}
MV_STATUS mvEthPhyLoopback(MV_U32 phyAddr, MV_BOOL isEnable)
{
MV_U16 regVal, ctrlVal;
MV_STATUS status;
/* Set loopback speed and duplex accordingly with current */
/* Bits: 6, 8, 13 */
if (mvEthPhyRegRead(phyAddr, ETH_PHY_CTRL_REG, &ctrlVal) != MV_OK)
return MV_FAIL;
if (isEnable) {
/* Select page 2 */
mvEthPhyRegWrite(phyAddr, 22, 2);
mvEthPhyRegRead(phyAddr, 21, ®Val);
regVal &= ~(ETH_PHY_CTRL_DUPLEX_MASK | ETH_PHY_CTRL_SPEED_LSB_MASK |
ETH_PHY_CTRL_SPEED_MSB_MASK | ETH_PHY_CTRL_AN_ENABLE_MASK);
regVal |= (ctrlVal & (ETH_PHY_CTRL_DUPLEX_MASK | ETH_PHY_CTRL_SPEED_LSB_MASK |
ETH_PHY_CTRL_SPEED_MSB_MASK | ETH_PHY_CTRL_AN_ENABLE_MASK));
mvEthPhyRegWrite(phyAddr, 21, regVal);
/* Select page 0 */
mvEthPhyRegWrite(phyAddr, 22, 0);
/* Disable Energy detection R16[9:8] = 00 */
/* Disable MDI/MDIX crossover R16[6:5] = 00 */
mvEthPhyRegRead(phyAddr, ETH_PHY_SPEC_CTRL_REG, ®Val);
regVal &= ~(BIT5 | BIT6 | BIT8 | BIT9);
mvEthPhyRegWrite(phyAddr, ETH_PHY_SPEC_CTRL_REG, regVal);
status = mvEthPhyReset(phyAddr, 1000);
if (status != MV_OK) {
mvOsPrintf("mvEthPhyReset failed: status=0x%x\n", status);
return status;
}
/* Set loopback */
ctrlVal |= ETH_PHY_CTRL_LOOPBACK_MASK;
mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, ctrlVal);
} else {
/* Cancel Loopback */
ctrlVal &= ~ETH_PHY_CTRL_LOOPBACK_MASK;
mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, ctrlVal);
status = mvEthPhyReset(phyAddr, 1000);
if (status != MV_OK) {
mvOsPrintf("mvEthPhyReset failed: status=0x%x\n", status);
return status;
}
/* Enable Energy detection R16[9:8] = 11 */
/* Enable MDI/MDIX crossover R16[6:5] = 11 */
mvEthPhyRegRead(phyAddr, ETH_PHY_SPEC_CTRL_REG, ®Val);
regVal |= (BIT5 | BIT6 | BIT8 | BIT9);
mvEthPhyRegWrite(phyAddr, ETH_PHY_SPEC_CTRL_REG, regVal);
status = mvEthPhyReset(phyAddr, 1000);
if (status != MV_OK) {
mvOsPrintf("mvEthPhyReset failed: status=0x%x\n", status);
return status;
}
}
return MV_OK;
}
/*******************************************************************************
* mvEthPhyPower -
*
* DESCRIPTION:
* Do a basic power down/up to the Phy , including reset
*
* INPUT:
* ethPortNum - Ethernet port number
* enable - MV_TRUE - power up
* MV_FALSE - power down
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
static MV_VOID mvEthPhyPower(MV_U32 ethPortNum, MV_BOOL enable)
{
MV_U16 reg;
if (enable == MV_FALSE) {
/* Power down command */
mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 2); /* select page 2 */
mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], 16, ®);
reg |= BIT3;
mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 16, reg); /* select to disable the SERDES */
mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 0); /* select page 0 */
mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 3); /* Power off LED's */
mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 16, 0x88);
mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 0);
mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], ETH_PHY_CTRL_REG, ®);
reg |= ETH_PHY_CTRL_RESET_MASK;
mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], ETH_PHY_CTRL_REG, reg); /* software reset */
mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], ETH_PHY_CTRL_REG, ®);
reg |= ETH_PHY_CTRL_POWER_DOWN_MASK;
mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], ETH_PHY_CTRL_REG, reg); /* power down the PHY */
} else {
/* Power up command */
mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 2); /* select page 2 */
mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], 16, ®);
reg &= ~BIT3;
mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 16, reg); /* select to enable the SERDES */
mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 0); /* select page 0 */
mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 3); /* Power on LED's */
mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 16, 0x03);
mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], 22, 0);
mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], ETH_PHY_CTRL_REG, ®);
reg |= ETH_PHY_CTRL_RESET_MASK;
mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], ETH_PHY_CTRL_REG, reg); /* software reset */
mvEthPhyRegRead(ethphyHalData.phyAddr[ethPortNum], ETH_PHY_CTRL_REG, ®);
reg &= ~ETH_PHY_CTRL_POWER_DOWN_MASK;
mvEthPhyRegWrite(ethphyHalData.phyAddr[ethPortNum], ETH_PHY_CTRL_REG, reg); /* power up the PHY */
}
}
