int evb_resource_dump_write(struct file *file, const char *buffer, unsigned long count, void *data)
{
/* Reading / Writing from system controller internal registers */
if (!strncmp(buffer, "register", 8)) {
if (buffer[10] == 'r') {
evb_resource_dump_request = atoh((char *)((unsigned int)buffer + 12), 8);
evb_resource_dump_result = MV_REG_READ(evb_resource_dump_request);
}
if (buffer[10] == 'w') {
evb_resource_dump_request = atoh((char *)((unsigned int)buffer + 12), 8);
evb_resource_dump_result = atoh((char *)((unsigned int)buffer + 12 + 8 + 1), 8);
MV_REG_WRITE(evb_resource_dump_request, evb_resource_dump_result);
}
}
/* Reading / Writing from 32bit address - mostly usable for memory */
if (!strncmp(buffer, "memory ", 8)) {
if (buffer[10] == 'r') {
evb_resource_dump_request = atoh((char *)((unsigned int)buffer + 12), 8);
evb_resource_dump_result = *(unsigned int *)evb_resource_dump_request;
}
if (buffer[10] == 'w') {
evb_resource_dump_request = atoh((char *)((unsigned int)buffer + 12), 8);
evb_resource_dump_result = atoh((char *)((unsigned int)buffer + 12 + 8 + 1), 8);
*(unsigned int *)evb_resource_dump_request = evb_resource_dump_result;
}
}
/* Reading / Writing from a rgister via SMI */
if (!strncmp(buffer, "smi", 3)) {
unsigned short regVal;
unsigned int dev_addr = atoh((char *)((unsigned int)buffer + 7), 8);
if (buffer[5] == 'r') {
evb_resource_dump_request = atoh((char *)((unsigned int)buffer + 7 + 8 + 1), 8);
regVal = 0;
mvEthPhyRegRead(dev_addr, evb_resource_dump_request, ®Val);
evb_resource_dump_result = (u32) regVal;
}
if (buffer[5] == 'w') {
evb_resource_dump_request = atoh((char *)((unsigned int)buffer + 7 + 8 + 1), 8);
evb_resource_dump_result = atoh((char *)((unsigned int)buffer + 7 + 8 + 8 + 2), 8);
mvEthPhyRegWrite(dev_addr, evb_resource_dump_request, (u16) evb_resource_dump_result);
}
}
#ifdef CONFIG_MV_CPU_PERF_CNTRS
if (!strncmp(buffer, "start_cc", 8)) {
int cc0, cc1, cc2, cc3;
sscanf((char *)((unsigned int)buffer + 8), "%d %d %d %d", &cc0, &cc1, &cc2, &cc3);
mv_proc_start_cntrs(cc0, cc1, cc2, cc3);
}
if (!strncmp(buffer, "show__cc", 8))
mv_proc_show_cntrs();
#endif /* */
#ifdef CONFIG_MV_CPU_L2_PERF_CNTRS
if (!strncmp(buffer, "start_l2", 8)) {
int l20, l21;
sscanf((char *)((unsigned int)buffer + 8), "%d %d", &l20, &l21);
mv_proc_start_l2_cntrs(l20, l21);
}
if (!strncmp(buffer, "show__l2", 8))
mv_proc_show_l2_cntrs();
#endif /* */
#ifdef CONFIG_MV_DRAM_STATS_CNTRS
if (!strncmp(buffer, "start_dram_stats", strlen("start_dram_stats"))) {
int mode0, mode1;
sscanf((char *)((unsigned int)buffer + strlen("start_dram_stats")), "%d %d", &mode0, &mode1);
mv_proc_start_dram_stats_cntrs(mode0, mode1);
}
if (!strncmp(buffer, "stop_dram_stats", strlen("stop_dram_stats")))
mvDramStatStop();
if (!strncmp(buffer, "show_dram_stats", strlen("show_dram_stats")))
mv_proc_show_dram_stats_cntrs();
#endif /* */
if (!strncmp(buffer, "idle_wfi", strlen("idle_wfi"))) {
int en;
sscanf((char *)((unsigned int)buffer + strlen("idle_wfi")), "%d", &en);
support_wait_for_interrupt = en;
}
if (!strncmp(buffer, "show__ua", 8)) {
if (kernel_align == 1)
kernel_align = 0;
else
kernel_align = 1;
printk(KERN_INFO "debug kernel align %d\n", kernel_align);
}
if (!strncmp(buffer, "cpu_freq", strlen("cpu_freq"))) {
buffer += strlen("cpu_freq") + 1;
if (!strncmp(buffer, "normal", strlen("normal"))) {
printk(KERN_INFO "Entering fast mode.\n");
mvCtrlPwrSaveOff();
} else if (!strncmp(buffer, "ddr", strlen("ddr"))) {
printk(KERN_INFO "Entering slow mode.\n");
mvCtrlPwrSaveOn();
}
}
#if 0
if (!strncmp(buffer, "ddd", 3)) {
unsigned int ii[10];
int ip, sum = 0;
volatile unsigned int *tt = (unsigned int *)((unsigned int)ii + 2);
MV_CPU_CNTRS_EVENT *hal_rx_event = NULL;
/* 0 - instruction counters */
mvCpuCntrsProgram(0, MV_CPU_CNTRS_INSTRUCTIONS, "Instr", 25);
/* 1 - ICache misses counter */
mvCpuCntrsProgram(1, MV_CPU_CNTRS_ICACHE_READ_MISS, "IcMiss", 0);
/* 2 - cycles counter */
mvCpuCntrsProgram(2, MV_CPU_CNTRS_CYCLES, "Cycles", 21);
/* 3 - DCache read misses counter */
mvCpuCntrsProgram(3, MV_CPU_CNTRS_DCACHE_READ_MISS, "DcRdMiss", 0);
hal_rx_event = mvCpuCntrsEventCreate("HAL_RX", 1);
MV_CPU_CNTRS_START(hal_rx_event);
for (ip = 0; ip < 1000; ip++)
sum += *tt;
MV_CPU_CNTRS_STOP(hal_rx_event);
MV_CPU_CNTRS_SHOW(hal_rx_event);
}
#endif /* */
return count;
}
int evb_resource_dump_write (struct file *file, const char *buffer,
unsigned long count, void *data) {
/* Reading / Writing from system controller internal registers */
if (!strncmp (buffer , "register" , 8)) {
if (buffer[10] == 'r') {
evb_resource_dump_request = atoh((char *)((unsigned int)buffer + 12),8);
evb_resource_dump_result = MV_REG_READ(evb_resource_dump_request);
}
if (buffer[10] == 'w') {
evb_resource_dump_request = atoh((char *)((unsigned int)buffer + 12), 8);
evb_resource_dump_result = atoh ((char *)((unsigned int)buffer + 12 + 8 + 1) , 8);
MV_REG_WRITE (evb_resource_dump_request , evb_resource_dump_result);
}
}
/* Reading / Writing from 32bit address - mostly usable for memory */
if (!strncmp (buffer , "memory " , 8)) {
if (buffer[10] == 'r') {
evb_resource_dump_request = atoh((char *)((unsigned int)buffer + 12),8);
evb_resource_dump_result = *(unsigned int *)evb_resource_dump_request;
}
if (buffer[10] == 'w') {
evb_resource_dump_request = atoh((char *)((unsigned int)buffer + 12), 8);
evb_resource_dump_result = atoh ((char *)((unsigned int)buffer + 12 + 8 + 1) , 8);
* (unsigned int *) evb_resource_dump_request = evb_resource_dump_result;
}
}
#if (defined (CONFIG_MV_ETHERNET) || defined (CONFIG_MV_GATEWAY)) && !defined(CONFIG_GTW_LOADABLE_DRV)
/* Reading / Writing from a rgister via SMI */
if (!strncmp (buffer , "smi" , 3)) {
unsigned int dev_addr = atoh((char *)((unsigned int)buffer + 7),8);
if (buffer[5] == 'r') {
evb_resource_dump_request = atoh((char *)((unsigned int)buffer + 7 + 8 + 1),8);
evb_resource_dump_result = 0;
#if defined (CONFIG_MV_ETHERNET)
mv_eth_read_mii(dev_addr, evb_resource_dump_request, &evb_resource_dump_result);
#elif defined (CONFIG_MV_GATEWAY)
mv_gtw_read_mii(NULL, dev_addr, evb_resource_dump_request, &evb_resource_dump_result);
#endif
}
if (buffer[5] == 'w') {
evb_resource_dump_request = atoh((char *)((unsigned int)buffer + 7 + 8 + 1), 8);
evb_resource_dump_result = atoh ((char *)((unsigned int)buffer + 7 + 8 + 8 + 2) , 8);
#if defined (CONFIG_MV_ETHERNET)
mv_eth_write_mii(dev_addr, evb_resource_dump_request , evb_resource_dump_result);
#elif defined (CONFIG_MV_GATEWAY)
mv_gtw_write_mii(NULL, dev_addr, evb_resource_dump_request , evb_resource_dump_result);
#endif
}
}
#endif
#ifdef CONFIG_MV_CPU_PERF_CNTRS
if (!strncmp (buffer , "start_cc" , 8)) {
int cc0, cc1, cc2, cc3;
sscanf( (char *)((unsigned int)buffer + 8),"%d %d %d %d",&cc0, &cc1, &cc2, &cc3 );
mv_proc_start_cntrs(cc0, cc1, cc2, cc3);
}
if (!strncmp (buffer , "show__cc" , 8)) {
mv_proc_show_cntrs();
}
#endif
#ifdef CONFIG_MV_CPU_L2_PERF_CNTRS
if (!strncmp (buffer , "start_l2" , 8)) {
int l20, l21;
sscanf( (char *)((unsigned int)buffer + 8),"%d %d",&l20, &l21);
mv_proc_start_l2_cntrs(l20, l21);
}
if (!strncmp (buffer , "show__l2" , 8)) {
mv_proc_show_l2_cntrs();
}
#endif
if(!strncmp (buffer , "show__ua" , 8)) {
if (kernel_align == 1)
kernel_align = 0;
else
kernel_align =1;
printk("debug kernel align %d\n",kernel_align);
}
#if 0
if(!strncmp (buffer , "ddd", 3)) {
unsigned int ii[10];
int ip, sum = 0;
volatile unsigned int *tt = (unsigned int*)((unsigned int)ii + 2);
MV_CPU_CNTRS_EVENT* hal_rx_event = NULL;
/* 0 - instruction counters */
mvCpuCntrsProgram(0, MV_CPU_CNTRS_INSTRUCTIONS, "Instr", 25);
/* 1 - ICache misses counter */
mvCpuCntrsProgram(1, MV_CPU_CNTRS_ICACHE_READ_MISS, "IcMiss", 0);
/* 2 - cycles counter */
mvCpuCntrsProgram(2, MV_CPU_CNTRS_CYCLES, "Cycles", 21);
/* 3 - DCache read misses counter */
mvCpuCntrsProgram(3, MV_CPU_CNTRS_DCACHE_READ_MISS, "DcRdMiss", 0);
hal_rx_event = mvCpuCntrsEventCreate("HAL_RX", 1);
MV_CPU_CNTRS_START(hal_rx_event);
for(ip = 0; ip < 1000; ip++) sum += *tt;
MV_CPU_CNTRS_STOP(hal_rx_event);
MV_CPU_CNTRS_SHOW(hal_rx_event);
}
#endif
return count;
}
