void gpio_can_active(int id)
{
int pad;
switch (id) {
case 0:
pad = PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | \
PAD_CTL_PUE_PUD | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH;
mxc_request_iomux(MX35_PIN_I2C2_CLK, MUX_CONFIG_ALT1);
mxc_request_iomux(MX35_PIN_I2C2_DAT, MUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX35_PIN_I2C2_CLK, pad);
mxc_iomux_set_pad(MX35_PIN_I2C2_DAT, pad);
mxc_iomux_set_input(MUX_IN_CAN1_CANRX, INPUT_CTL_PATH0);
break;
case 1:
pad = PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU;
mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_ALT1);
mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad);
mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad);
mxc_iomux_set_input(MUX_IN_CAN2_CANRX, INPUT_CTL_PATH2);
break;
default:
printk(KERN_ERR "NO such device\n");
}
}
/***************************************
* update_flag=0, BOOT_NORMAL
* update_flag=1, BOOT_SYSTEM_UPGRADE
* update_flag=2, BOOT_OTA
****************************************/
int recovery_handle(void)
{
unsigned int val = 0;
unsigned int reg1 = 0;
unsigned int reg2 = 0;
struct spi_slave *slave;
if (share_region->flags.uboot_flag != BOOT_NORMAL)
goto out;
/* No power key any more*/
#if 0
slave = spi_pmic_probe();
val = pmic_reg(slave, 3, 0, 0);
val = (val & 0x000004) >> 2;
#endif
mxc_request_iomux(MX50_PIN_KEY_COL3, IOMUX_CONFIG_ALT1);
mxc_request_iomux(MX50_PIN_KEY_ROW0, IOMUX_CONFIG_ALT1);
reg1 = readl(GPIO4_BASE_ADDR);
reg1 &= 0x00000040;
reg2 = readl(GPIO4_BASE_ADDR);
reg2 &= 0x00000002;
#if 0
printf("val = %d\n", val);
if ((reg1 && reg2) != 1 && (val == 1))
clear_flags();
#endif
if (1 == (reg1 && reg2))
share_region->flags.uboot_flag = BOOT_SYSTEM_UPGRADE;
out:
save_share_region();
printf("share_region = %d\n", share_region->flags.uboot_flag);
return share_region->flags.uboot_flag;
}
/*!
* Setup GPIO for Keypad to be active
*
*/
void gpio_keypad_active(void)
{
#if 0
int pad_val;
/*
* Configure the IOMUX control register for keypad signals.
*/
/*KEY_INT */
mxc_request_iomux(MX37_PIN_GPIO1_3, IOMUX_CONFIG_ALT0);
/*KEY_WAKE */
mxc_request_iomux(MX37_PIN_DISP1_DAT18, IOMUX_CONFIG_ALT4);
/* fast slew rate */
pad_val = (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_22K_PU | \
PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_HYS_NONE | \
PAD_CTL_DDR_INPUT_CMOS | PAD_CTL_DRV_VOT_LOW);
/*KEY_INT */
mxc_iomux_set_pad(MX37_PIN_GPIO1_3, pad_val);
/* fast slew rate */
pad_val = (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | \
PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_HYS_NONE | \
PAD_CTL_DDR_INPUT_CMOS | PAD_CTL_DRV_VOT_LOW);
/*KEY_WAKE */
mxc_iomux_set_pad(MX37_PIN_DISP1_DAT18, pad_val);
mxc_set_gpio_direction(MX37_PIN_DISP1_DAT18, 0);
mxc_set_gpio_direction(MX37_PIN_GPIO1_3, 1);
/* drive initial value */
mxc_set_gpio_dataout(MX37_PIN_DISP1_DAT18, 1);
#endif
}
void board_ehci_hcd_init(int port)
{
/* Set USBH1_STP to GPIO and toggle it */
mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO);
mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
gpio_direction_output(MX51EVK_USBH1_STP, 0);
gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
mdelay(10);
gpio_set_value(MX51EVK_USBH1_STP, 1);
/* Set back USBH1_STP to be function */
mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
/* De-assert USB PHY RESETB */
gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
/* Drive USB_CLK_EN_B line low */
gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
/* Reset USB hub */
gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
mdelay(2);
gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
}
/*
* Configure the USB H1 and USB H2 IOMUX
*/
void setup_iomux_usb(void)
{
setup_iomux_usb_h1();
if (machine_is_efikasb())
setup_iomux_usb_h2();
/* USB PHY reset */
mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE |
PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
/* USB HUB reset */
mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE |
PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
/* WIFI EN (act low) */
mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO);
mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0);
/* WIFI RESET */
mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO);
mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0);
/* BT EN (act low) */
mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO);
mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0);
}
/*!
* Setup GPIO for an I2C device to be inactive
*
* @param i2c_num an I2C device
*/
void gpio_i2c_inactive(int i2c_num)
{
switch (i2c_num) {
case 0:
mxc_free_iomux(MX31_PIN_I2C_CLK, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_free_iomux(MX31_PIN_I2C_DAT, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
break;
case 1:
mxc_free_iomux(MX31_PIN_CSPI2_MOSI, OUTPUTCONFIG_FUNC,
INPUTCONFIG_ALT1);
mxc_free_iomux(MX31_PIN_CSPI2_MISO, OUTPUTCONFIG_FUNC,
INPUTCONFIG_ALT1);
break;
case 2:
mxc_request_iomux(MX31_PIN_CSPI2_SS2, OUTPUTCONFIG_FUNC,
INPUTCONFIG_ALT1);
mxc_request_iomux(MX31_PIN_CSPI2_SCLK, OUTPUTCONFIG_FUNC,
INPUTCONFIG_ALT1);
break;
default:
break;
}
}
void mx50_yoshi_gpio_spi_chipselect_active(int cspi_mode, int status,
int chipselect)
{
switch (cspi_mode) {
case 1:
break;
case 2:
break;
case 3:
switch (chipselect) {
case 0x1:
/* enable ss0 */
mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_ALT0);
/*disable other ss */
mxc_request_iomux(MX50_PIN_ECSPI1_MOSI, IOMUX_CONFIG_GPIO);
/* pull up/down deassert it */
gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_ECSPI1_MOSI));
break;
case 0x2:
/* enable ss1 */
mxc_request_iomux(MX50_PIN_ECSPI1_MOSI, IOMUX_CONFIG_ALT2);
/*disable other ss */
mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_GPIO);
/* pull up/down deassert it */
gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_CSPI_SS0));
break;
default:
break;
}
break;
default:
break;
}
}
/*
* Board identification
*/
u32 get_efikamx_rev(void)
{
u32 rev = 0;
/*
* Retrieve board ID:
* rev1.1: 1,1,1
* rev1.2: 1,1,0
* rev1.3: 1,0,1
* rev1.4: 1,0,0
*/
mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
/* set to 1 in order to get correct value on board rev1.1 */
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1);
mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU);
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0));
rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0;
mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO);
mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU);
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1));
rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1;
mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO);
mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU);
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3));
rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2;
return (~rev & 0x7) + 1;
}
void gpio_epdc_pins_enable(int enable)
{
if (enable == 0) {
mxc_free_iomux(MX50_PIN_EPDC_SDCE0, IOMUX_CONFIG_ALT0);
mxc_free_iomux(MX50_PIN_EPDC_GDSP, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX50_PIN_EPDC_SDCE0, IOMUX_CONFIG_ALT1);
mxc_request_iomux(MX50_PIN_EPDC_GDSP, IOMUX_CONFIG_ALT1);
gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_SDCE0), "epdc_sdce0");
gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EPDC_SDCE0), 0);
gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_GDSP), "epdc_gdsp");
gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EPDC_GDSP), 0);
gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_EPDC_SDCE0), 0);
gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_EPDC_GDSP), 0);
}
else {
mxc_free_iomux(MX50_PIN_EPDC_SDCE0, IOMUX_CONFIG_ALT1);
mxc_free_iomux(MX50_PIN_EPDC_GDSP, IOMUX_CONFIG_ALT1);
mxc_request_iomux(MX50_PIN_EPDC_SDCE0, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX50_PIN_EPDC_GDSP, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX50_PIN_EPDC_SDCE0, PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE);
mxc_iomux_set_pad(MX50_PIN_EPDC_GDSP, PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE);
}
}
void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status,
int chipselect)
{
switch (cspi_mode) {
case 1:
switch (chipselect) {
case 0x1:
mxc_free_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4);
mxc_request_iomux(MX53_PIN_EIM_D19,
IOMUX_CONFIG_GPIO);
mxc_free_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_GPIO);
mxc_free_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4);
break;
case 0x2:
mxc_free_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4);
mxc_request_iomux(MX53_PIN_EIM_EB2,
IOMUX_CONFIG_GPIO);
mxc_free_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_GPIO);
mxc_free_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4);
break;
default:
break;
}
break;
case 2:
break;
case 3:
break;
default:
break;
}
}
void gpio_i2c_inactive(int i2c_num)
{
if (i2c_num == 0) {
mxc_free_iomux(MX50_PIN_I2C1_SCL, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_request_iomux(MX50_PIN_I2C1_SCL, IOMUX_CONFIG_ALT1);
gpio_request(IOMUX_TO_GPIO(MX50_PIN_I2C1_SCL), "i2c1_scl");
gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_I2C1_SCL));
mxc_free_iomux(MX50_PIN_I2C1_SDA, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_request_iomux(MX50_PIN_I2C1_SDA, IOMUX_CONFIG_ALT1);
gpio_request(IOMUX_TO_GPIO(MX50_PIN_I2C1_SDA), "i2c1_sda");
gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_I2C1_SDA));
}
if (i2c_num == 1) {
mxc_free_iomux(MX50_PIN_I2C2_SCL, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_request_iomux(MX50_PIN_I2C2_SCL, IOMUX_CONFIG_ALT1);
gpio_request(IOMUX_TO_GPIO(MX50_PIN_I2C2_SCL), "i2c2_scl");
gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_I2C2_SCL));
mxc_free_iomux(MX50_PIN_I2C2_SDA, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_request_iomux(MX50_PIN_I2C2_SDA, IOMUX_CONFIG_ALT1);
gpio_request(IOMUX_TO_GPIO(MX50_PIN_I2C2_SDA), "i2c_sda");
gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_I2C2_SDA));
}
}
void gpio_i2s_enable(void)
{
unsigned int pad_val;
pad_val = PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
mxc_free_iomux(MX37_PIN_AUD5_WB_CK, IOMUX_CONFIG_ALT4);
mxc_iomux_set_pad(MX37_PIN_AUD5_WB_CK, PAD_CTL_100K_PU | pad_val);
mxc_request_iomux(MX37_PIN_AUD5_WB_CK, IOMUX_CONFIG_ALT0);
mxc_free_iomux(MX37_PIN_AUD5_WB_RXD, IOMUX_CONFIG_ALT4);
mxc_iomux_set_pad(MX37_PIN_AUD5_WB_RXD, pad_val);
mxc_request_iomux(MX37_PIN_AUD5_WB_RXD, IOMUX_CONFIG_ALT0);
mxc_free_iomux(MX37_PIN_AUD5_WB_TXD, IOMUX_CONFIG_ALT4);
mxc_iomux_set_pad(MX37_PIN_AUD5_WB_TXD, pad_val);
mxc_request_iomux(MX37_PIN_AUD5_WB_TXD, IOMUX_CONFIG_ALT0);
mxc_free_iomux(MX37_PIN_AUD5_WB_FS, IOMUX_CONFIG_ALT4);
mxc_iomux_set_pad(MX37_PIN_AUD5_WB_FS, PAD_CTL_100K_PU | pad_val);
mxc_request_iomux(MX37_PIN_AUD5_WB_FS, IOMUX_CONFIG_ALT0);
/* Enable hysteresis for AUD5_WB_CK, AUD5_WB_RXD, AUD5_WB_TXD, AUD5_WB_FS */
mxc_iomux_set_pad(MX37_PIN_GRP_H5, PAD_CTL_HYS_ENABLE);
}
/*!
* Setup GPIO for a CSPI device to be inactive
*
* @param cspi_mod a CSPI device
*/
void gpio_spi_inactive(int cspi_mod)
{
switch (cspi_mod) {
case 0:
break;
case 1:
break;
case 2:
/* SPI3 */
mxc_free_iomux(MX37_PIN_SD2_CMD, IOMUX_CONFIG_ALT2); //MOSI
mxc_free_iomux(MX37_PIN_SD2_CLK, IOMUX_CONFIG_ALT2); //SCLK
mxc_free_iomux(MX37_PIN_SD2_DATA0, IOMUX_CONFIG_ALT2);//MISO
mxc_free_iomux(MX37_PIN_SD2_DATA3, IOMUX_CONFIG_ALT2);//SS1
mxc_request_iomux(MX37_PIN_SD2_CMD, IOMUX_CONFIG_ALT3);
mxc_request_iomux(MX37_PIN_SD2_DATA0, IOMUX_CONFIG_ALT3);
mxc_request_iomux(MX37_PIN_SD2_CLK, IOMUX_CONFIG_ALT3);
mxc_request_iomux(MX37_PIN_SD2_DATA3, IOMUX_CONFIG_ALT3);
mxc_set_gpio_direction(MX37_PIN_SD2_CMD, 1);
mxc_set_gpio_direction(MX37_PIN_SD2_DATA0, 1);
mxc_set_gpio_direction(MX37_PIN_SD2_CLK, 1);
mxc_set_gpio_direction(MX37_PIN_SD2_DATA3, 1);
mxc_free_iomux(MX37_PIN_SD2_CMD, IOMUX_CONFIG_ALT3);
mxc_free_iomux(MX37_PIN_SD2_CLK, IOMUX_CONFIG_ALT3);
mxc_free_iomux(MX37_PIN_SD2_DATA0, IOMUX_CONFIG_ALT3);
mxc_free_iomux(MX37_PIN_SD2_DATA3, IOMUX_CONFIG_ALT3);
break;
default:
break;
}
}
/*
* USB Host1 HS port
*/
static int gpio_usbh1_active(void)
{
/* Set USBH1_STP to GPIO and toggle it */
mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO |
IOMUX_CONFIG_SION);
gpio_request(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), "usbh1_stp");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 1);
/* Signal only used on MX51-3DS for reset to PHY.*/
if (machine_is_mx51_3ds()) {
mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX51_PIN_EIM_D17, PAD_CTL_DRV_HIGH |
PAD_CTL_HYS_NONE | PAD_CTL_PUE_KEEPER |
PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_D17), "eim_d17");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D17), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D17), 1);
}
msleep(100);
return 0;
}
static void setup_iomux_spi(void)
{
mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
}
void gpio_activate_audio_ports(void)
{
/* Setup audio port 4 */
mxc_request_iomux(MX31_PIN_SCK4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_SRXD4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_STXD4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_SFS4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
}
static void si4702_gpio_get(void)
{
/* reset pin */
mxc_request_iomux(MX31_PIN_SRST0, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
mxc_set_gpio_direction(MX31_PIN_SRST0, 0);
mxc_request_iomux(MX31_PIN_SIMPD0, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
mxc_set_gpio_direction(MX31_PIN_SIMPD0, 0);
}
/*!
* Setup GPIO for Keypad to be inactive
*
*/
void gpio_keypad_inactive(void)
{
#if 0
/*KEY_INT */
mxc_request_iomux(MX37_PIN_GPIO1_3, IOMUX_CONFIG_ALT0);
/*KEY_WAKE */
mxc_request_iomux(MX37_PIN_DISP1_DAT18, IOMUX_CONFIG_ALT0);
#endif
}
/*
* USB OTG UTMI
*/
int gpio_usbotg_utmi_active(void)
{
mxc_request_iomux(MX35_PIN_USBOTG_PWR, MUX_CONFIG_FUNC);
mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, 0x0040);
mxc_request_iomux(MX35_PIN_USBOTG_OC, MUX_CONFIG_FUNC);
mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, 0x01c0);
return 0;
}
/* setup GPIO for mma7450 */
static void gpio_mma7450_get(void)
{
mxc_request_iomux(MX31_PIN_STX0, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO);
mxc_iomux_set_pad(MX31_PIN_STX0, PAD_CTL_PKE_NONE);
mxc_set_gpio_direction(MX31_PIN_STX0, 1);
mxc_request_iomux(MX31_PIN_SRX0, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO);
mxc_iomux_set_pad(MX31_PIN_SRX0, PAD_CTL_PKE_NONE);
mxc_set_gpio_direction(MX31_PIN_SRX0, 1);
}
/* workaround for ecspi chipselect pin may not keep correct level when idle */
void mx53_evk_gpio_spi_chipselect_active(int cspi_mode, int status,
int chipselect)
{
switch (cspi_mode) {
case 1:
switch (chipselect) {
case 0x1:
/* de-select SS1 of instance: ecspi1. */
mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX53_PIN_EIM_D19,
PAD_CTL_HYS_ENABLE |
PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PULL |
PAD_CTL_100K_PU |
PAD_CTL_DRV_HIGH);
/* mux mode: ALT4 mux port: SS0 of instance: ecspi1. */
mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4);
mxc_iomux_set_pad(MX53_PIN_EIM_EB2,
PAD_CTL_HYS_ENABLE |
PAD_CTL_DRV_HIGH);
mxc_iomux_set_input(
MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
INPUT_CTL_PATH3);
break;
case 0x2:
/* de-select SS0 of instance: ecspi1. */
mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX53_PIN_EIM_EB2,
PAD_CTL_HYS_ENABLE |
PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PULL |
PAD_CTL_100K_PU |
PAD_CTL_DRV_HIGH);
mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4);
mxc_iomux_set_pad(MX53_PIN_EIM_D19,
PAD_CTL_HYS_ENABLE |
PAD_CTL_DRV_HIGH);
mxc_iomux_set_input(
MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
INPUT_CTL_PATH3);
break;
default:
break;
}
break;
case 2:
break;
case 3:
break;
default:
break;
}
}
static void si4702_gpio_get(void)
{
/* reset pin */
mxc_request_iomux(MX31_PIN_SRST0, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
gpio_request(IOMUX_TO_GPIO(MX31_PIN_SRST0), "srst0");
gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_SRST0), 0);
mxc_request_iomux(MX31_PIN_SIMPD0, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
gpio_request(IOMUX_TO_GPIO(MX31_PIN_SIMPD0), "simpd0");
gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_SIMPD0), 0);
}
static void setup_uart(void)
{
unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
/* console RX on Pin EIM_D25 */
mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad);
/* console TX on Pin EIM_D26 */
mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad);
}
/*
* USB Host2
*/
int gpio_usbh2_active(void)
{
mxc_request_iomux(MX35_PIN_I2C2_CLK, MUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX35_PIN_I2C2_CLK, 0x0040);
mxc_request_iomux(MX35_PIN_I2C2_DAT, MUX_CONFIG_ALT2);
mxc_iomux_set_input(MUX_IN_USB_UH2_USB_OC, INPUT_CTL_PATH0);
mxc_iomux_set_pad(MX35_PIN_I2C2_DAT, 0x01c0);
return 0;
}
/*!
* Setup GPIO for spdif tx/rx to be active
*/
void gpio_spdif_active(void)
{
/* SPDIF OUT */
mxc_request_iomux(MX35_PIN_STXD5, MUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX35_PIN_STXD5, PAD_CTL_PKE_NONE | PAD_CTL_PUE_PUD);
/* SPDIF IN */
mxc_request_iomux(MX35_PIN_SRXD5, MUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX35_PIN_SRXD5, PAD_CTL_PKE_ENABLE
| PAD_CTL_100K_PU | PAD_CTL_HYS_SCHMITZ);
/* SPDIF ext clock */
mxc_request_iomux(MX35_PIN_SCK5, MUX_CONFIG_ALT1);
}
/* setup GPIO for mma7450 */
static void gpio_mma7450_get(void)
{
mxc_request_iomux(MX31_PIN_STX0, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO);
mxc_iomux_set_pad(MX31_PIN_STX0, PAD_CTL_PKE_NONE);
gpio_request(IOMUX_TO_GPIO(MX31_PIN_STX0), "stx0");
gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_STX0));
mxc_request_iomux(MX31_PIN_SRX0, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO);
mxc_iomux_set_pad(MX31_PIN_SRX0, PAD_CTL_PKE_NONE);
gpio_request(IOMUX_TO_GPIO(MX31_PIN_SRX0), "srx0");
gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SRX0));
}
/*!
* Setup GPIO for a CSPI device to be active
*
* @param cspi_mod an CSPI device
*/
void gpio_spi_active(int cspi_mod)
{
switch (cspi_mod) {
case 0:
break;
case 1:
#if 0
/* SPI2 */
mxc_request_iomux(MX37_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX37_PIN_CSPI2_MISO, PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX37_PIN_GRP_H9, PAD_CTL_HYS_ENABLE);
mxc_request_iomux(MX37_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX37_PIN_CSPI2_MOSI, PAD_CTL_SRE_FAST);
mxc_request_iomux(MX37_PIN_UART1_CTS, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX37_PIN_UART1_CTS, PAD_CTL_HYS_ENABLE |
PAD_CTL_PKE_ENABLE);
mxc_request_iomux(MX37_PIN_CSPI2_SCLK, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX37_PIN_CSPI2_SCLK, PAD_CTL_HYS_ENABLE |
PAD_CTL_SRE_FAST);
mxc_request_iomux(MX37_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX37_PIN_CSPI2_SS1, PAD_CTL_SRE_FAST);
mxc_request_iomux(MX37_PIN_CSPI2_SS0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX37_PIN_CSPI2_SS0, PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX37_PIN_GRP_H10, PAD_CTL_HYS_ENABLE);
#endif
break;
case 2:
/* SPI3 */
mxc_request_iomux(MX37_PIN_SD2_CMD, IOMUX_CONFIG_ALT2); //MOSI
mxc_iomux_set_pad(MX37_PIN_SD2_CMD,PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
mxc_request_iomux(MX37_PIN_SD2_CLK, IOMUX_CONFIG_ALT2); //SCLK
mxc_iomux_set_pad(MX37_PIN_SD2_CMD,PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
mxc_request_iomux(MX37_PIN_SD2_DATA0, IOMUX_CONFIG_ALT2);//MISO
mxc_iomux_set_pad(MX37_PIN_SD2_CMD,PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
mxc_request_iomux(MX37_PIN_SD2_DATA3, IOMUX_CONFIG_ALT2);//SS1
mxc_iomux_set_pad(MX37_PIN_SD2_CMD,PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
break;
default:
break;
}
}
static void setup_iomux_fec(void)
{
/*FEC_MDIO*/
mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
/*FEC_MDC*/
mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
/* FEC RXD1 */
mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
/* FEC RXD0 */
mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
/* FEC TXD1 */
mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
/* FEC TXD0 */
mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
/* FEC TX_EN */
mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
/* FEC TX_CLK */
mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
/* FEC RX_ER */
mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
/* FEC CRS */
mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
}
static void setup_iomux_uart(void)
{
unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
}
int board_mmc_getcd(u8 *cd, struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1);
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
*cd = gpio_get_value(1); /*GPIO1_1*/
else
*cd = gpio_get_value(4); /*GPIO1_4*/
return 0;
}
