static int mxl111sf_ep6_streaming_ctrl(struct dvb_frontend *fe, int onoff)
{
struct mxl111sf_state *state = fe_to_priv(fe);
struct mxl111sf_adap_state *adap_state = &state->adap_state[fe->id];
int ret = 0;
deb_info("%s(%d)\n", __func__, onoff);
if (onoff) {
ret = mxl111sf_enable_usb_output(state);
mxl_fail(ret);
ret = mxl111sf_config_mpeg_in(state, 1, 1,
adap_state->ep6_clockphase,
0, 0);
mxl_fail(ret);
#if 0
} else {
ret = mxl111sf_disable_656_port(state);
mxl_fail(ret);
#endif
}
return ret;
}
static int mxl111sf_tuner_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u32 delsys = c->delivery_system;
struct mxl111sf_tuner_state *state = fe->tuner_priv;
int ret;
u8 bw;
mxl_dbg("()");
switch (delsys) {
case SYS_ATSC:
case SYS_ATSCMH:
bw = 0; /* ATSC */
break;
case SYS_DVBC_ANNEX_B:
bw = 1; /* US CABLE */
break;
case SYS_DVBT:
switch (c->bandwidth_hz) {
case 6000000:
bw = 6;
break;
case 7000000:
bw = 7;
break;
case 8000000:
bw = 8;
break;
default:
err("%s: bandwidth not set!", __func__);
return -EINVAL;
}
break;
default:
err("%s: modulation type not supported!", __func__);
return -EINVAL;
}
ret = mxl1x1sf_tune_rf(fe, c->frequency, bw);
if (mxl_fail(ret))
goto fail;
state->frequency = c->frequency;
state->bandwidth = c->bandwidth_hz;
fail:
return ret;
}
static int mxl111sf_tuner_get_status(struct dvb_frontend *fe, u32 *status)
{
struct mxl111sf_tuner_state *state = fe->tuner_priv;
int rf_locked, ref_locked, ret;
*status = 0;
ret = mxl1x1sf_tuner_get_lock_status(state, &rf_locked, &ref_locked);
if (mxl_fail(ret))
goto fail;
mxl_info("%s%s", rf_locked ? "rf locked " : "",
ref_locked ? "ref locked" : "");
if ((rf_locked) || (ref_locked))
*status |= TUNER_STATUS_LOCKED;
fail:
return ret;
}
static int mxl1x1sf_tuner_get_lock_status(struct mxl111sf_tuner_state *state,
int *rf_synth_lock,
int *ref_synth_lock)
{
int ret;
u8 data;
*rf_synth_lock = 0;
*ref_synth_lock = 0;
ret = mxl111sf_tuner_read_reg(state, V6_RF_LOCK_STATUS_REG, &data);
if (mxl_fail(ret))
goto fail;
*ref_synth_lock = ((data & 0x03) == 0x03) ? 1 : 0;
*rf_synth_lock = ((data & 0x0c) == 0x0c) ? 1 : 0;
fail:
return ret;
}
int mxl111sf_ctrl_msg(struct dvb_usb_device *d,
u8 cmd, u8 *wbuf, int wlen, u8 *rbuf, int rlen)
{
int wo = (rbuf == NULL || rlen == 0); /* write-only */
int ret;
u8 sndbuf[1+wlen];
deb_adv("%s(wlen = %d, rlen = %d)\n", __func__, wlen, rlen);
memset(sndbuf, 0, 1+wlen);
sndbuf[0] = cmd;
memcpy(&sndbuf[1], wbuf, wlen);
ret = (wo) ? dvb_usbv2_generic_write(d, sndbuf, 1+wlen) :
dvb_usbv2_generic_rw(d, sndbuf, 1+wlen, rbuf, rlen);
mxl_fail(ret);
return ret;
}
int mxl111sf_ctrl_program_regs(struct mxl111sf_state *state,
struct mxl111sf_reg_ctrl_info *ctrl_reg_info)
{
int i, ret = 0;
for (i = 0; ctrl_reg_info[i].addr |
ctrl_reg_info[i].mask |
ctrl_reg_info[i].data; i++) {
ret = mxl111sf_write_reg_mask(state,
ctrl_reg_info[i].addr,
ctrl_reg_info[i].mask,
ctrl_reg_info[i].data);
if (mxl_fail(ret)) {
err("failed on reg #%d (0x%02x)", i,
ctrl_reg_info[i].addr);
break;
}
}
return ret;
}
int mxl111sf_read_reg(struct mxl111sf_state *state, u8 addr, u8 *data)
{
u8 buf[2];
int ret;
ret = mxl111sf_ctrl_msg(state->d, MXL_CMD_REG_READ, &addr, 1, buf, 2);
if (mxl_fail(ret)) {
mxl_debug("error reading reg: 0x%02x", addr);
goto fail;
}
if (buf[0] == addr)
*data = buf[1];
else {
err("invalid response reading reg: 0x%02x != 0x%02x, 0x%02x",
addr, buf[0], buf[1]);
ret = -EINVAL;
}
deb_reg("R: (0x%02x, 0x%02x)\n", addr, *data);
fail:
return ret;
}
static void mxl5007t_set_bw_bits(struct mxl5007t_state *state,
enum mxl5007t_bw_mhz bw)
{
u8 val;
switch (bw) {
case MxL_BW_6MHz:
val = 0x15; /* set DIG_MODEINDEX, DIG_MODEINDEX_A,
* and DIG_MODEINDEX_CSF */
break;
case MxL_BW_7MHz:
val = 0x21;
break;
case MxL_BW_8MHz:
val = 0x3f;
break;
default:
mxl_fail(-EINVAL);
return;
}
set_reg_bits(state->tab_rftune, 0x13, 0x3f, val);
return;
}
static
int mxl1x1sf_demod_get_tps_guard_fft_mode(struct mxl111sf_demod_state *state,
enum fe_transmit_mode *fft_mode)
{
u8 val;
int ret = mxl111sf_demod_read_reg(state, V6_MODE_TPS_REG, &val);
/* FFT Mode, 00:2K, 01:8K, 10:4K */
if (mxl_fail(ret))
goto fail;
switch ((val & V6_PARAM_FFT_MODE_MASK) >> 2) {
case 0:
*fft_mode = TRANSMISSION_MODE_2K;
break;
case 1:
*fft_mode = TRANSMISSION_MODE_8K;
break;
case 2:
*fft_mode = TRANSMISSION_MODE_4K;
break;
}
fail:
return ret;
}
static
int mxl1x1sf_demod_get_tps_modulation(struct mxl111sf_demod_state *state,
enum fe_modulation *modulation)
{
u8 val;
int ret = mxl111sf_demod_read_reg(state, V6_MODORDER_TPS_REG, &val);
/* Constellation, 00 : QPSK, 01 : 16QAM, 10:64QAM */
if (mxl_fail(ret))
goto fail;
switch ((val & V6_PARAM_CONSTELLATION_MASK) >> 4) {
case 0:
*modulation = QPSK;
break;
case 1:
*modulation = QAM_16;
break;
case 2:
*modulation = QAM_64;
break;
}
fail:
return ret;
}
static int mxl111sf_lg2161_ep6_frontend_attach(struct dvb_usb_adapter *adap, u8 fe_id)
{
struct dvb_usb_device *d = adap_to_d(adap);
struct mxl111sf_state *state = d_to_priv(d);
struct mxl111sf_adap_state *adap_state = &state->adap_state[fe_id];
int ret;
deb_adv("%s()\n", __func__);
/* save a pointer to the dvb_usb_device in device state */
state->d = d;
adap_state->alt_mode = (dvb_usb_mxl111sf_isoc) ? 2 : 1;
state->alt_mode = adap_state->alt_mode;
if (usb_set_interface(d->udev, 0, state->alt_mode) < 0)
err("set interface failed");
state->gpio_mode = MXL111SF_GPIO_MOD_MH;
adap_state->gpio_mode = state->gpio_mode;
adap_state->device_mode = MXL_TUNER_MODE;
adap_state->ep6_clockphase = 0;
ret = mxl1x1sf_soft_reset(state);
if (mxl_fail(ret))
goto fail;
ret = mxl111sf_init_tuner_demod(state);
if (mxl_fail(ret))
goto fail;
ret = mxl1x1sf_set_device_mode(state, adap_state->device_mode);
if (mxl_fail(ret))
goto fail;
ret = mxl111sf_enable_usb_output(state);
if (mxl_fail(ret))
goto fail;
ret = mxl1x1sf_top_master_ctrl(state, 1);
if (mxl_fail(ret))
goto fail;
ret = mxl111sf_init_port_expander(state);
if (mxl_fail(ret))
goto fail;
ret = mxl111sf_gpio_mode_switch(state, state->gpio_mode);
if (mxl_fail(ret))
goto fail;
ret = get_chip_info(state);
if (mxl_fail(ret))
goto fail;
adap->fe[fe_id] = dvb_attach(lg2160_attach,
(MXL111SF_V8_200 == state->chip_rev) ?
&hauppauge_lg2161_1040_ep6_config :
&hauppauge_lg2161_1019_ep6_config,
&d->i2c_adap);
if (adap->fe[fe_id]) {
state->num_frontends++;
adap_state->fe_init = adap->fe[fe_id]->ops.init;
adap->fe[fe_id]->ops.init = mxl111sf_adap_fe_init;
adap_state->fe_sleep = adap->fe[fe_id]->ops.sleep;
adap->fe[fe_id]->ops.sleep = mxl111sf_adap_fe_sleep;
return 0;
}
ret = -EIO;
fail:
return ret;
}
static int mxl1x1sf_tuner_set_if_output_freq(struct mxl111sf_tuner_state *state)
{
int ret;
u8 ctrl;
#if 0
u16 iffcw;
u32 if_freq;
#endif
mxl_dbg("(IF polarity = %d, IF freq = 0x%02x)",
state->cfg->invert_spectrum, state->cfg->if_freq);
/* set IF polarity */
ctrl = state->cfg->invert_spectrum;
ctrl |= state->cfg->if_freq;
ret = mxl111sf_tuner_write_reg(state, V6_TUNER_IF_SEL_REG, ctrl);
if (mxl_fail(ret))
goto fail;
#if 0
if_freq /= 1000000;
/* do round */
if_freq += 0.5;
if (MXL_IF_LO == state->cfg->if_freq) {
ctrl = 0x08;
iffcw = (u16)(if_freq / (108 * 4096));
} else if (MXL_IF_HI == state->cfg->if_freq) {
ctrl = 0x08;
iffcw = (u16)(if_freq / (216 * 4096));
} else {
ctrl = 0;
iffcw = 0;
}
ctrl |= (iffcw >> 8);
#endif
ret = mxl111sf_tuner_read_reg(state, V6_TUNER_IF_FCW_BYP_REG, &ctrl);
if (mxl_fail(ret))
goto fail;
ctrl &= 0xf0;
ctrl |= 0x90;
ret = mxl111sf_tuner_write_reg(state, V6_TUNER_IF_FCW_BYP_REG, ctrl);
if (mxl_fail(ret))
goto fail;
#if 0
ctrl = iffcw & 0x00ff;
#endif
ret = mxl111sf_tuner_write_reg(state, V6_TUNER_IF_FCW_REG, ctrl);
if (mxl_fail(ret))
goto fail;
state->if_freq = state->cfg->if_freq;
fail:
return ret;
}
static void mxl5007t_set_mode_bits(struct mxl5007t_state *state,
enum mxl5007t_mode mode,
s32 if_diff_out_level)
{
switch (mode) {
case MxL_MODE_OTA_DVBT_ATSC:
set_reg_bits(state->tab_init, 0x32, 0x0f, 0x06);
set_reg_bits(state->tab_init, 0x35, 0xff, 0x0e);
break;
case MxL_MODE_OTA_ISDBT:
set_reg_bits(state->tab_init, 0x32, 0x0f, 0x06);
set_reg_bits(state->tab_init, 0x35, 0xff, 0x12);
break;
case MxL_MODE_OTA_NTSC_PAL_GH:
set_reg_bits(state->tab_init, 0x16, 0x70, 0x00);
set_reg_bits(state->tab_init, 0x32, 0xff, 0x85);
break;
case MxL_MODE_OTA_PAL_IB:
set_reg_bits(state->tab_init, 0x16, 0x70, 0x10);
set_reg_bits(state->tab_init, 0x32, 0xff, 0x85);
break;
case MxL_MODE_OTA_PAL_D_SECAM_KL:
set_reg_bits(state->tab_init, 0x16, 0x70, 0x20);
set_reg_bits(state->tab_init, 0x32, 0xff, 0x85);
break;
case MxL_MODE_CABLE_DIGITAL:
set_reg_bits(state->tab_init_cable, 0x71, 0xff, 0x01);
set_reg_bits(state->tab_init_cable, 0x72, 0xff,
8 - if_diff_out_level);
set_reg_bits(state->tab_init_cable, 0x74, 0xff, 0x17);
break;
case MxL_MODE_CABLE_NTSC_PAL_GH:
set_reg_bits(state->tab_init, 0x16, 0x70, 0x00);
set_reg_bits(state->tab_init, 0x32, 0xff, 0x85);
set_reg_bits(state->tab_init_cable, 0x71, 0xff, 0x01);
set_reg_bits(state->tab_init_cable, 0x72, 0xff,
8 - if_diff_out_level);
set_reg_bits(state->tab_init_cable, 0x74, 0xff, 0x17);
break;
case MxL_MODE_CABLE_PAL_IB:
set_reg_bits(state->tab_init, 0x16, 0x70, 0x10);
set_reg_bits(state->tab_init, 0x32, 0xff, 0x85);
set_reg_bits(state->tab_init_cable, 0x71, 0xff, 0x01);
set_reg_bits(state->tab_init_cable, 0x72, 0xff,
8 - if_diff_out_level);
set_reg_bits(state->tab_init_cable, 0x74, 0xff, 0x17);
break;
case MxL_MODE_CABLE_PAL_D_SECAM_KL:
set_reg_bits(state->tab_init, 0x16, 0x70, 0x20);
set_reg_bits(state->tab_init, 0x32, 0xff, 0x85);
set_reg_bits(state->tab_init_cable, 0x71, 0xff, 0x01);
set_reg_bits(state->tab_init_cable, 0x72, 0xff,
8 - if_diff_out_level);
set_reg_bits(state->tab_init_cable, 0x74, 0xff, 0x17);
break;
case MxL_MODE_CABLE_SCTE40:
set_reg_bits(state->tab_init_cable, 0x36, 0xff, 0x08);
set_reg_bits(state->tab_init_cable, 0x68, 0xff, 0xbc);
set_reg_bits(state->tab_init_cable, 0x71, 0xff, 0x01);
set_reg_bits(state->tab_init_cable, 0x72, 0xff,
8 - if_diff_out_level);
set_reg_bits(state->tab_init_cable, 0x74, 0xff, 0x17);
break;
default:
mxl_fail(-EINVAL);
}
return;
}
/* initialize TSIF as input port of MxL1X1SF for MPEG2 data transfer */
int mxl111sf_config_mpeg_in(struct mxl111sf_state *state,
unsigned int parallel_serial,
unsigned int msb_lsb_1st,
unsigned int clock_phase,
unsigned int mpeg_valid_pol,
unsigned int mpeg_sync_pol)
{
int ret;
u8 mode, tmp;
mxl_debug("(%u,%u,%u,%u,%u)", parallel_serial, msb_lsb_1st,
clock_phase, mpeg_valid_pol, mpeg_sync_pol);
/* Enable PIN MUX */
ret = mxl111sf_write_reg(state, V6_PIN_MUX_MODE_REG, V6_ENABLE_PIN_MUX);
mxl_fail(ret);
/* Configure MPEG Clock phase */
mxl111sf_read_reg(state, V6_MPEG_IN_CLK_INV_REG, &mode);
if (clock_phase == TSIF_NORMAL)
mode &= ~V6_INVERTED_CLK_PHASE;
else
mode |= V6_INVERTED_CLK_PHASE;
ret = mxl111sf_write_reg(state, V6_MPEG_IN_CLK_INV_REG, mode);
mxl_fail(ret);
/* Configure data input mode, MPEG Valid polarity, MPEG Sync polarity
* Get current configuration */
ret = mxl111sf_read_reg(state, V6_MPEG_IN_CTRL_REG, &mode);
mxl_fail(ret);
/* Data Input mode */
if (parallel_serial == TSIF_INPUT_PARALLEL) {
/* Disable serial mode */
mode &= ~V6_MPEG_IN_DATA_SERIAL;
/* Enable Parallel mode */
mode |= V6_MPEG_IN_DATA_PARALLEL;
} else {
/* Disable Parallel mode */
mode &= ~V6_MPEG_IN_DATA_PARALLEL;
/* Enable Serial Mode */
mode |= V6_MPEG_IN_DATA_SERIAL;
/* If serial interface is chosen, configure
MSB or LSB order in transmission */
ret = mxl111sf_read_reg(state,
V6_MPEG_INOUT_BIT_ORDER_CTRL_REG,
&tmp);
mxl_fail(ret);
if (msb_lsb_1st == MPEG_SER_MSB_FIRST_ENABLED)
tmp |= V6_MPEG_SER_MSB_FIRST;
else
tmp &= ~V6_MPEG_SER_MSB_FIRST;
ret = mxl111sf_write_reg(state,
V6_MPEG_INOUT_BIT_ORDER_CTRL_REG,
tmp);
mxl_fail(ret);
}
/* MPEG Sync polarity */
if (mpeg_sync_pol == TSIF_NORMAL)
mode &= ~V6_INVERTED_MPEG_SYNC;
else
mode |= V6_INVERTED_MPEG_SYNC;
/* MPEG Valid polarity */
if (mpeg_valid_pol == 0)
mode &= ~V6_INVERTED_MPEG_VALID;
else
mode |= V6_INVERTED_MPEG_VALID;
ret = mxl111sf_write_reg(state, V6_MPEG_IN_CTRL_REG, mode);
mxl_fail(ret);
return ret;
}
static void mxl5007t_set_xtal_freq_bits(struct mxl5007t_state *state,
enum mxl5007t_xtal_freq xtal_freq)
{
switch (xtal_freq)
{
case MxL_XTAL_16_MHZ:
/* select xtal freq & ref freq */
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x00);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x00);
break;
case MxL_XTAL_20_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x10);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x01);
break;
case MxL_XTAL_20_25_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x20);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x02);
break;
case MxL_XTAL_20_48_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x30);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x03);
break;
case MxL_XTAL_24_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x40);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x04);
break;
case MxL_XTAL_25_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x50);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x05);
break;
case MxL_XTAL_25_14_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x60);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x06);
break;
case MxL_XTAL_27_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x70);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x07);
break;
case MxL_XTAL_28_8_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x80);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x08);
break;
case MxL_XTAL_32_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0x90);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x09);
break;
case MxL_XTAL_40_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0xa0);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0a);
break;
case MxL_XTAL_44_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0xb0);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0b);
break;
case MxL_XTAL_48_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0xc0);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0c);
break;
case MxL_XTAL_49_3811_MHZ:
set_reg_bits(state->tab_init, 0x03, 0xf0, 0xd0);
set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0d);
break;
default:
mxl_fail(-EINVAL);
return;
}
return;
}
