/* * Initializes the NFC hardware. */ int mxs_nand_init(struct mxs_nand_info *info) { struct mxs_gpmi_regs *gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE; struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; int i = 0, j, ret = 0; info->desc = malloc(sizeof(struct mxs_dma_desc *) * MXS_NAND_DMA_DESCRIPTOR_COUNT); if (!info->desc) { ret = -ENOMEM; goto err1; } /* Allocate the DMA descriptors. */ for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) { info->desc[i] = mxs_dma_desc_alloc(); if (!info->desc[i]) { ret = -ENOMEM; goto err2; } } /* Init the DMA controller. */ mxs_dma_init(); for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0; j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) { ret = mxs_dma_init_channel(j); if (ret) goto err3; } /* Reset the GPMI block. */ mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg); mxs_reset_block(&bch_regs->hw_bch_ctrl_reg); /* * Choose NAND mode, set IRQ polarity, disable write protection and * select BCH ECC. */ clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1, GPMI_CTRL1_GPMI_MODE, GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET | GPMI_CTRL1_BCH_MODE); return 0; err3: for (--j; j >= MXS_DMA_CHANNEL_AHB_APBH_GPMI0; j--) mxs_dma_release(j); err2: for (--i; i >= 0; i--) mxs_dma_desc_free(info->desc[i]); free(info->desc); err1: if (ret == -ENOMEM) printf("MXS NAND: Unable to allocate DMA descriptors\n"); return ret; }
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)) { struct mmc *mmc = NULL; struct mxsmmc_priv *priv = NULL; int ret; const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id); if (!mxs_ssp_bus_id_valid(id)) return -ENODEV; priv = malloc(sizeof(struct mxsmmc_priv)); if (!priv) return -ENOMEM; priv->desc = mxs_dma_desc_alloc(); if (!priv->desc) { free(priv); return -ENOMEM; } ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id); if (ret) return ret; priv->mmc_is_wp = wp; priv->mmc_cd = cd; priv->id = id; priv->regs = mxs_ssp_regs_by_bus(id); priv->cfg.name = "MXS MMC"; priv->cfg.ops = &mxsmmc_ops; priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS; /* * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), * CLOCK_DIVIDE has to be an even value from 2 to 254, and * CLOCK_RATE could be any integer from 0 to 255. */ priv->cfg.f_min = 400000; priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2; priv->cfg.b_max = 0x20; mmc = mmc_create(&priv->cfg, priv); if (mmc == NULL) { mxs_dma_desc_free(priv->desc); free(priv); return -ENOMEM; } return 0; }
/* * Initializes the NFC hardware. */ int mxs_nand_init(struct mxs_nand_info *info) { int ret; int i; info->desc = malloc(sizeof(struct mxs_dma_desc *) * MXS_NAND_DMA_DESCRIPTOR_COUNT); if (!info->desc) { printf("MXS NAND: Unable to allocate DMA descriptor table\n"); ret = -ENOMEM; goto err1; } mxs_dma_init(); /* Allocate the DMA descriptors. */ for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) { info->desc[i] = mxs_dma_desc_alloc(); if (!info->desc[i]) { printf("MXS NAND: Unable to allocate DMA descriptors\n"); ret = -ENOMEM; goto err2; } } /* Init the DMA controller. */ for (i = 0; i < CONFIG_SYS_NAND_MAX_CHIPS; i++) { const int chan = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + i; ret = mxs_dma_init_channel(chan); if (ret) { printf("Failed to initialize DMA channel %d\n", chan); goto err3; } } ret = mxs_nand_gpmi_init(); if (ret) goto err3; return 0; err3: for (--i; i >= 0; i--) mxs_dma_release(i + MXS_DMA_CHANNEL_AHB_APBH_GPMI0); i = MXS_NAND_DMA_DESCRIPTOR_COUNT - 1; err2: free(info->desc); for (--i; i >= 0; i--) mxs_dma_desc_free(info->desc[i]); err1: return ret; }
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; struct mmc *mmc = NULL; struct mxsmmc_priv *priv = NULL; int ret; mmc = malloc(sizeof(struct mmc)); if (!mmc) return -ENOMEM; priv = malloc(sizeof(struct mxsmmc_priv)); if (!priv) { free(mmc); return -ENOMEM; } priv->desc = mxs_dma_desc_alloc(); if (!priv->desc) { free(priv); free(mmc); return -ENOMEM; } ret = mxs_dma_init_channel(id); if (ret) return ret; priv->mmc_is_wp = wp; priv->id = id; switch (id) { case 0: priv->regs = (struct mxs_ssp_regs *)MXS_SSP0_BASE; priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0; priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0; break; case 1: priv->regs = (struct mxs_ssp_regs *)MXS_SSP1_BASE; priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1; priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1; break; case 2: priv->regs = (struct mxs_ssp_regs *)MXS_SSP2_BASE; priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2; priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2; break; case 3: priv->regs = (struct mxs_ssp_regs *)MXS_SSP3_BASE; priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3; priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3; break; } sprintf(mmc->name, "MXS MMC"); mmc->send_cmd = mxsmmc_send_cmd; mmc->set_ios = mxsmmc_set_ios; mmc->init = mxsmmc_init; mmc->getcd = NULL; mmc->priv = priv; mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS; /* * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), * CLOCK_DIVIDE has to be an even value from 2 to 254, and * CLOCK_RATE could be any integer from 0 to 255. */ mmc->f_min = 400000; mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2; mmc->b_max = 0x20; mmc_register(mmc); return 0; }
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)) { struct mmc *mmc = NULL; struct mxsmmc_priv *priv = NULL; int ret; #if defined(CONFIG_MX23) const unsigned int mxsmmc_max_id = 2; const unsigned int mxsmmc_clk_id = 0; #elif defined(CONFIG_MX28) const unsigned int mxsmmc_max_id = 4; const unsigned int mxsmmc_clk_id = id; #endif if (id >= mxsmmc_max_id) return -ENODEV; mmc = malloc(sizeof(struct mmc)); if (!mmc) return -ENOMEM; priv = malloc(sizeof(struct mxsmmc_priv)); if (!priv) { free(mmc); return -ENOMEM; } priv->desc = mxs_dma_desc_alloc(); if (!priv->desc) { free(priv); free(mmc); return -ENOMEM; } ret = mxs_dma_init_channel(id + mxsmmc_id_offset); if (ret) return ret; priv->mmc_is_wp = wp; priv->mmc_cd = cd; priv->id = id; priv->regs = mxs_ssp_regs_by_bus(id); sprintf(mmc->name, "MXS MMC"); mmc->send_cmd = mxsmmc_send_cmd; mmc->set_ios = mxsmmc_set_ios; mmc->init = mxsmmc_init; mmc->getcd = NULL; mmc->priv = priv; mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS; /* * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), * CLOCK_DIVIDE has to be an even value from 2 to 254, and * CLOCK_RATE could be any integer from 0 to 255. */ mmc->f_min = 400000; mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2; mmc->b_max = 0x20; mmc_register(mmc); return 0; }