void board_init_r(gd_t *id, ulong dummy)
{
nand_init();
puts("Nand boot...\n");
nand_boot();
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *)CONFIG_SPL_GD_ADDR;
bd_t *bd;
memset(gd, 0, sizeof(gd_t));
bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
bd->bi_memsize = CONFIG_SYS_L2_SIZE;
probecpu();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
#ifndef CONFIG_SPL_NAND_BOOT
env_init();
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_initialize(bd);
#endif
/* relocate environment function pointers etc. */
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
gd->env_valid = 1;
#else
env_relocate();
#endif
#ifdef CONFIG_SYS_I2C
i2c_init_all();
#else
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
gd->ram_size = initdram(0);
#ifdef CONFIG_SPL_NAND_BOOT
puts("Tertiary program loader running in sram...");
#else
puts("Second program loader running in sram...\n");
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
}
void board_init_f(unsigned long bootflag)
{
//mem_malloc_init (0xa00000, 0x100000);
writel(readl(REG_PCLKEN0) | 0x10000, REG_PCLKEN0); // UART clk
writel(readl(REG_PCLKEN0) | 0x100, REG_PCLKEN0); // Timer clk
nuc970_serial_initialize();
nuc970_serial_init();
printf("nand_boot\n");
nand_boot();
//relocate_code(CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
//CONFIG_SYS_TEXT_BASE);
}
static int do_boota(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned long mmc_select,mem_address,sectors;
/* Consume 'boota' */
argc--; argv++;
if (argc < 2)
return CMD_RET_USAGE;
if (!strcmp("mem",argv[0])) {
mem_address=simple_strtoul(argv[1], NULL, 16);
printf("mem boot start\n");
mem_boot(mem_address);
printf("mem boot error\n");
} else if (!strcmp("mmc",argv[0])) {
mmc_select=simple_strtoul(argv[1], NULL, 10);
mem_address=simple_strtoul(argv[2], NULL, 16);
sectors=simple_strtoul(argv[3], NULL, 10);
#ifdef CONFIG_SPL_MMC_SUPPORT
printf("MSC boot start\n");
mmc_ready(mmc_select);
msc_boot(mmc_select,mem_address,sectors);
printf("MSC boot error\n");
return 0;
#else /*!CONFIG_SPL_MMC_SUPPORT */
} else if (!strcmp("nand",argv[0])) {
mem_address=simple_strtoul(argv[1], NULL, 16);
sectors=simple_strtoul(argv[2], NULL, 10);
printf("Nand boot start\n");
nand_ready();
nand_boot(mem_address,sectors);
printf("Nand boot error\n");
return 0;
#endif/*!CONFIG_SPL_MMC_SUPPORT*/
} else {
printf("%s boot unsupport\n", argv[0]);
return CMD_RET_USAGE;
}
return 0;
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *)CONFIG_SPL_GD_ADDR;
bd_t *bd;
memset(gd, 0, sizeof(gd_t));
bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
bd->bi_memsize = CONFIG_SYS_L2_SIZE;
arch_cpu_init();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
/* relocate environment function pointers etc. */
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
gd->env_valid = ENV_VALID;
i2c_init_all();
dram_init();
#ifdef CONFIG_SPL_NAND_BOOT
puts("TPL\n");
#else
puts("SPL\n");
#endif
nand_boot();
}
/***********************************************************************
*
* Function: autoboot
*
* Purpose: Autoload an image
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: FALSE if the operation failed, otherwise TRUE.
*
* Notes: None
*
**********************************************************************/
BOOL_32 autoboot(void)
{
BOOL_32 loaded = FALSE;
switch (syscfg.aboot.abootsrc)
{
case SRC_TERM:
loaded = term_boot();
break;
case SRC_BLKDEV:
loaded = blk_boot();
break;
case SRC_NAND:
loaded = nand_boot();
break;
default:
break;
}
return loaded;
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
puts("SPL\n");
nand_boot();
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
nand_boot();
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
puts("\nSecond program loader running in sram...");
nand_boot();
}
void nand_spl_init(void)
{
ulong buffer[6];
u8 page_buf[CONFIG_NAND_PAGE_SIZE];
ulong ddr_magic=0x88888888;
ulong erase_addr1=0, erase_addr2=0;
ulong ecc;
int i;
erase_addr1 = IFX_CFG_FLASH_DDR_CFG_START_ADDR;
erase_addr2 = IFX_CFG_FLASH_DDR_CFG_START_ADDR + IFX_CFG_FLASH_DDR_CFG_SIZE;
serial_init();
buffer[0] = 0;
asm("sync");
nand_read_page((131072/CONFIG_NAND_PAGE_SIZE)-1,page_buf);
asm("sync");
for(i=0; i<6; i++) {
buffer[i] = *(volatile u32*)(page_buf+CONFIG_NAND_PAGE_SIZE-24+i*4); /*last 24 bytes of 16k bytes*/
}
if(buffer[0]==ddr_magic)
{
ecc=buffer[1]^buffer[2]^buffer[3]^buffer[4];
if(ecc!=buffer[5]) {
REG32(0xBe1a7f20)=0xff;
} else {
REG32(0xBe1a7f20)=0;
}
}
else {
REG32(0xBe1a7f20)=0xff;
}
/* Clear Error log registers */
REG32(MC_ERRCAUSE)= 0;
REG32(MC_ERRADDR) = 0;
asm("sync");
/* Enable DDR module in memory controller */
REG32(MC_CON)= REG32(MC_CON)|MC_DDRRAM_ENABLE;
asm("sync");
if(REG32(0xBe1a7f20)==0xff) {
REG32(MC_DC21)= 0;
REG32(MC_DC22)=0;
} else {
REG32(MC_DC15)= buffer[1];
REG32(MC_DC21)= buffer[2];
REG32(MC_DC22)= buffer[3];
REG32(MC_DC24)= buffer[4];
}
asm("sync");
REG32(MC_DC03) = 0x00000100;
while((REG32(0xbf800070)& 0x08)!=0x08);
asm("sync");
tune_ddr();
asm("sync");
nand_boot();
}
