static int nv84_crypt_init(struct nouveau_object *object) { struct nv84_crypt_priv *priv = (void *)object; int ret; ret = nouveau_engine_init(&priv->base); if (ret) return ret; nv_wr32(priv, 0x102130, 0xffffffff); nv_wr32(priv, 0x102140, 0xffffffbf); nv_wr32(priv, 0x10200c, 0x00000010); return 0; }
int _nouveau_xtensa_init(struct nouveau_object *object) { struct nouveau_device *device = nv_device(object); struct nouveau_xtensa *xtensa = (void *)object; const struct firmware *fw; char name[32]; int i, ret; u32 tmp; ret = nouveau_engine_init(&xtensa->base); if (ret) return ret; if (!xtensa->gpu_fw) { snprintf(name, sizeof(name), "nouveau/nv84_xuc%03x", xtensa->addr >> 12); ret = request_firmware(&fw, name, nv_device_base(device)); if (ret) { nv_warn(xtensa, "unable to load firmware %s\n", name); return ret; } if (fw->size > 0x40000) { nv_warn(xtensa, "firmware %s too large\n", name); release_firmware(fw); return -EINVAL; } ret = nouveau_gpuobj_new(object, NULL, 0x40000, 0x1000, 0, &xtensa->gpu_fw); if (ret) { release_firmware(fw); return ret; } nv_debug(xtensa, "Loading firmware to address: 0x%"PRIxMAX"\n", (uintmax_t)xtensa->gpu_fw->addr); for (i = 0; i < fw->size / 4; i++) nv_wo32(xtensa->gpu_fw, i * 4, *((u32 *)fw->data + i)); release_firmware(fw); }
int _nouveau_falcon_init(struct nouveau_object *object) { struct nouveau_device *device = nv_device(object); struct nouveau_falcon *falcon = (void *)object; const struct firmware *fw; char name[32] = "internal"; int ret, i; u32 caps; /* enable engine, and determine its capabilities */ ret = nouveau_engine_init(&falcon->base); if (ret) return ret; if (device->chipset < 0xa3 || device->chipset == 0xaa || device->chipset == 0xac) { falcon->version = 0; falcon->secret = (falcon->addr == 0x087000) ? 1 : 0; } else { caps = nv_ro32(falcon, 0x12c); falcon->version = (caps & 0x0000000f); falcon->secret = (caps & 0x00000030) >> 4; } caps = nv_ro32(falcon, 0x108); falcon->code.limit = (caps & 0x000001ff) << 8; falcon->data.limit = (caps & 0x0003fe00) >> 1; nv_debug(falcon, "falcon version: %d\n", falcon->version); nv_debug(falcon, "secret level: %d\n", falcon->secret); nv_debug(falcon, "code limit: %d\n", falcon->code.limit); nv_debug(falcon, "data limit: %d\n", falcon->data.limit); /* wait for 'uc halted' to be signalled before continuing */ if (falcon->secret && falcon->version < 4) { if (!falcon->version) nv_wait(falcon, 0x008, 0x00000010, 0x00000010); else nv_wait(falcon, 0x180, 0x80000000, 0); nv_wo32(falcon, 0x004, 0x00000010); } /* disable all interrupts */ nv_wo32(falcon, 0x014, 0xffffffff); /* no default ucode provided by the engine implementation, try and * locate a "self-bootstrapping" firmware image for the engine */ if (!falcon->code.data) { snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03x", device->chipset, falcon->addr >> 12); ret = request_firmware(&fw, name, &device->pdev->dev); if (ret == 0) { falcon->code.data = kmemdup(fw->data, fw->size, GFP_KERNEL); falcon->code.size = fw->size; falcon->data.data = NULL; falcon->data.size = 0; release_firmware(fw); } falcon->external = true; }