void __init ixdp2800_init_irq(void)
{
int i = 0;
*IXDP2800_CPLD_INT_MASK = 0; /* turn off interrupts */
/* initialize chip specific interrupts */
ixp2000_init_irq();
/*
* Slave only has NIC routed to it, so we don't init everything
*/
if (npu_is_master()) {
for(i = NR_IXP2000_IRQS; i < NR_IXDP2800_IRQS; i++) {
irq_desc[i].valid = 1;
irq_desc[i].probe_ok = 0;
irq_desc[i].mask_ack = ext_irq_mask;
irq_desc[i].mask = ext_irq_mask;
irq_desc[i].unmask = ext_irq_unmask;
}
/* init PCI interrupts */
setup_arm_irq(IRQ_IXP2000_PCIB, &ext_irq);
}
}
/*
* We only do anything if we are the master NPU on the board.
* The slave NPU only has the ethernet chip going directly to
* the PCIB interrupt input.
*/
void __init ixdp2400_init_irq(void)
{
int i = 0;
/* initialize chip specific interrupts */
ixp2000_init_irq();
if (npu_is_master()) {
/* Disable all CPLD interrupts */
acquire_slowport(&slowport_cpld_cfg);
*IXDP2400_CPLD_INT_MASK = 0xff;
release_slowport();
for(i = NR_IXP2000_IRQS; i < NR_IXDP2400_IRQS; i++) {
irq_desc[i].valid = 1;
irq_desc[i].probe_ok = 0;
irq_desc[i].mask_ack = ext_irq_mask;
irq_desc[i].mask = ext_irq_mask;
irq_desc[i].unmask = ext_irq_unmask;
}
/* Hook into PCI interrupts */
setup_arm_irq(IRQ_IXP2000_PCIB, &ext_irq);
}
}
void __init ixp2000_pci_init(void *sysdata)
{
external_fault = ixp2000_pci_abort_handler;
DBG("PCI: set upper mem io bits\n");
*IXP2000_PCI_ADDR_EXT = 0x0;
if (npu_is_master()) {/* master NPU */
pci_scan_bus(0, &ixp2000_ops, sysdata);
} else { /* NPU is slave */
/*
* NOTE TO HW DESIGNERS:
*
* Do NOT make boards like this which have slave devices that scan
* the bus and own devices. It is completely against the PCI spec
* as it is _NOT_ a peer to peer bus.
*/
if(machine_is_ixdp2400())
pci_scan_bus(0, &ixp2000_ops, sysdata);
}
/* enable PCI INTB */
*(IXP2000_IRQ_ENABLE_SET) = (1<<15);
*IXP2000_PCI_XSCALE_INT_ENABLE |= (1<<27) | (1<<26);
DBG("ixp200_pci_init Done\n");
}
/*
* This board does not do normal PCI IRQ routing, or any
* sort of swizzling, so we just need to check where on the
* bus the device is and figure out what CPLD pin it's
* being routed to.
*/
static int __init
ixdp2800_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
if (npu_is_master()) {
/*
* Root bus devices. Slave NPU is only one with interrupt.
* Everything else, we just return -1 which is invalid.
*/
if(!dev->bus->self) {
if(dev->devfn == 0x0028 )
return IRQ_IXDP2800_INGRESS_NPU;
return -1;
}
/*
* We have a bridge behind the PMC slot
* NOTE: Only INTA from the PMC slot is routed.
*/
if(PCI_SLOT(dev->bus->self->devfn) == 0x7 &&
PCI_SLOT(dev->bus->parent->self->devfn) == 0x4 &&
!dev->bus->parent->self->bus->parent)
return IRQ_IXDP2800_PMC_PCI;
/*
* Device behind the first bridge
*/
if(PCI_SLOT(dev->bus->self->devfn) == 0x4) {
switch(PCI_SLOT(dev->devfn)) {
case 0x2: // Master PMC
return IRQ_IXDP2800_PMC_PCI;
case 0x3: // Ethernet
return IRQ_IXDP2800_EGRESS_NIC;
case 0x5: // Switch fabric
return IRQ_IXDP2800_FABRIC;
}
}
return 0;
} else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */
}
void __init ixdp2800_pci_init(void *sysdata)
{
ixp2000_pci_init(sysdata);
*IXP2000_PCI_CMDSTAT = 0;
*IXP2000_PCI_ADDR_EXT = 0x0000e000;
*IXP2000_PCI_DRAM_BASE_ADDR_MASK = (0x20000000 - 1) & ~0xfffff;
*IXP2000_PCI_SRAM_BASE_ADDR_MASK = (0x40000 - 1) & ~0x3ffff;
DBG("allocating hose\n");
hose = pcibios_alloc_controller();
if (!hose)
panic("Could not allocate PCI hose");
hose->first_busno = 0;
hose->last_busno = 0;
hose->io_space.start = 0x00000000;
hose->io_space.end = 0x0000ffff;
hose->mem_space.start = 0xe0000000;
hose->mem_space.end = 0xffffffff;
/*
* Scan bus and exclude devices depending on whether we are the
* master or slave NPU. Sigh...
*
* NOTE TO HW DESIGNERS: DO NOT PUT MULTIPLE PCI HOST CPUS
* ON THE SAME BUS SEGMENT. THAT'S WHAT NON-TRANSPARENT
* BRIDGES ARE FOR.
*/
if (npu_is_master()) {
DBG("setup BARS\n");
*IXP2000_PCI_SDRAM_BAR = PHYS_OFFSET;
*IXP2000_PCI_CMDSTAT = (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* autoconfig the bus */
DBG("AUTOCONFIG\n");
hose->last_busno = pciauto_bus_scan(hose, 0);
/* scan the bus */
DBG("SCANNING THE BUS\n");
pci_scan_bus(0,&ixp2000_ops, sysdata);
pci_exclude_device(0x01, 0x20); /* Remove slave's NIC*/
pci_exclude_device(0x0, 0x38); /* Remove self XXX FIXME*/
} else {
/* Wait for the master NPU to enable us */
while(!(*IXP2000_PCI_CMDSTAT & PCI_COMMAND_MASTER));
pci_scan_bus(0,&ixp2000_ops, sysdata);
int i;
pci_exclude_device(0x01, 0x38); /* Remove PMC site */
pci_exclude_device(0x01, 0x18); /* Remove master NIC*/
pci_exclude_device(0x0, 0x20); /* Remove remove 21154*/
pci_exclude_device(0x0, 0x30); /* Remove 21555*/
pci_exclude_device(0x0, 0x28); /* Remove Self XXX FIXME */
/*
* need to keep for IXA SDK support
*/
#if 0
pci_exclude_device(0x0, 0x38); /* Remove Master IXP*/
#endif
/*
* In case there's a bridge on the PMC, we remove everything
* on bus 2.
*/
for(i = 0; i < 0xff; i++)
pci_exclude_device(0x2, i);
}
}
