static int nordicsemi_nrf52_init(struct device *arg) { u32_t key; ARG_UNUSED(arg); key = irq_lock(); SystemInit(); #ifdef CONFIG_NRF_ENABLE_ICACHE /* Enable the instruction cache */ NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk; #endif #if defined(CONFIG_SOC_DCDC_NRF52X) nrf_power_dcdcen_set(true); #endif _ClearFaults(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); irq_unlock(key); return 0; }
nrfx_err_t nrfx_power_init(nrfx_power_config_t const * p_config) { NRFX_ASSERT(p_config); if (m_initialized) { return NRFX_ERROR_ALREADY_INITIALIZED; } #if NRF_POWER_HAS_VDDH nrf_power_dcdcen_vddh_set(p_config->dcdcenhv); #endif nrf_power_dcdcen_set(p_config->dcdcen); nrfx_power_clock_irq_init(); m_initialized = true; return NRFX_SUCCESS; }