Esempio n. 1
0
File: nv94.c Progetto: 3null/linux
static int
nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	       struct nouveau_oclass *oclass, void *data, u32 size,
	       struct nouveau_object **pobject)
{
	struct nv50_disp_priv *priv;
	int ret;

	ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
				  "display", &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
	if (ret)
		return ret;

	nv_engine(priv)->sclass = nv94_disp_base_oclass;
	nv_engine(priv)->cclass = &nv50_disp_cclass;
	nv_subdev(priv)->intr = nv50_disp_intr;
	INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
	priv->sclass = nv94_disp_sclass;
	priv->head.nr = 2;
	priv->dac.nr = 3;
	priv->sor.nr = 4;
	priv->pior.nr = 3;
	priv->dac.power = nv50_dac_power;
	priv->dac.sense = nv50_dac_sense;
	priv->sor.power = nv50_sor_power;
	priv->sor.hdmi = nv84_hdmi_ctrl;
	priv->pior.power = nv50_pior_power;
	return 0;
}
Esempio n. 2
0
File: nv10.c Progetto: 24hours/linux
static int
nv10_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	       struct nouveau_oclass *oclass, void *data, u32 size,
	       struct nouveau_object **pobject)
{
	struct nv04_instmem_priv *imem = nv04_instmem(parent);
	struct nv04_fifo_priv *priv;
	int ret;

	ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	nouveau_ramht_ref(imem->ramht, &priv->ramht);
	nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
	nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);

	nv_subdev(priv)->unit = 0x00000100;
	nv_subdev(priv)->intr = nv04_fifo_intr;
	nv_engine(priv)->cclass = &nv10_fifo_cclass;
	nv_engine(priv)->sclass = nv10_fifo_sclass;
	priv->base.pause = nv04_fifo_pause;
	priv->base.start = nv04_fifo_start;
	priv->ramfc_desc = nv10_ramfc;
	return 0;
}
Esempio n. 3
0
static int
nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	       struct nouveau_oclass *oclass, void *data, u32 size,
	       struct nouveau_object **pobject)
{
	struct nv50_disp_priv *priv;
	int heads = nv_rd32(parent, 0x022448);
	int ret;

	ret = nouveau_disp_create(parent, engine, oclass, heads,
				  "PDISP", "display", &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	nv_engine(priv)->sclass = nvf0_disp_base_oclass;
	nv_engine(priv)->cclass = &nv50_disp_cclass;
	nv_subdev(priv)->intr = nvd0_disp_intr;
	INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
	priv->sclass = nvf0_disp_sclass;
	priv->head.nr = heads;
	priv->dac.nr = 3;
	priv->sor.nr = 4;
	priv->dac.power = nv50_dac_power;
	priv->dac.sense = nv50_dac_sense;
	priv->sor.power = nv50_sor_power;
	priv->sor.hda_eld = nvd0_hda_eld;
	priv->sor.hdmi = nvd0_hdmi_ctrl;
	return 0;
}
Esempio n. 4
0
static int
nv25_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	       struct nouveau_oclass *oclass, void *data, u32 size,
	       struct nouveau_object **pobject)
{
	struct nv20_graph_priv *priv;
	int ret;

	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_new(parent, NULL, 32 * 4, 16,
				 NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
	if (ret)
		return ret;

	nv_subdev(priv)->unit = 0x00001000;
	nv_subdev(priv)->intr = nv20_graph_intr;
	nv_engine(priv)->cclass = &nv25_graph_cclass;
	nv_engine(priv)->sclass = nv25_graph_sclass;
	nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
	return 0;
}
Esempio n. 5
0
File: gf100.c Progetto: 168519/linux
static int
gf100_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
	      struct nvkm_oclass *oclass, void *data, u32 size,
	      struct nvkm_object **pobject)
{
	struct gf100_pm_priv *priv;
	u32 mask;
	int ret;

	ret = nvkm_pm_create(parent, engine, oclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	ret = nvkm_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, gf100_pm_pwr);
	if (ret)
		return ret;

	/* HUB */
	ret = nvkm_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
			       gf100_pm_hub);
	if (ret)
		return ret;

	/* GPC */
	mask  = (1 << nv_rd32(priv, 0x022430)) - 1;
	mask &= ~nv_rd32(priv, 0x022504);
	mask &= ~nv_rd32(priv, 0x022584);

	ret = nvkm_perfdom_new(&priv->base, "gpc", mask, 0x180000,
			       0x1000, 0x200, gf100_pm_gpc);
	if (ret)
		return ret;

	/* PART */
	mask  = (1 << nv_rd32(priv, 0x022438)) - 1;
	mask &= ~nv_rd32(priv, 0x022548);
	mask &= ~nv_rd32(priv, 0x0225c8);

	ret = nvkm_perfdom_new(&priv->base, "part", mask, 0x1a0000,
			       0x1000, 0x200, gf100_pm_part);
	if (ret)
		return ret;

	nv_engine(priv)->cclass = &nvkm_pm_cclass;
	nv_engine(priv)->sclass =  nvkm_pm_sclass;
	priv->base.last = 7;
	return 0;
}
Esempio n. 6
0
File: nv50.c Progetto: 24hours/linux
static int
nv50_disp_data_ctor(struct nouveau_object *parent,
		    struct nouveau_object *engine,
		    struct nouveau_oclass *oclass, void *data, u32 size,
		    struct nouveau_object **pobject)
{
	struct nv50_disp_priv *priv = (void *)engine;
	struct nouveau_engctx *ectx;
	int ret = -EBUSY;

	/* no context needed for channel objects... */
	if (nv_mclass(parent) != NV_DEVICE_CLASS) {
		atomic_inc(&parent->refcount);
		*pobject = parent;
		return 1;
	}

	/* allocate display hardware to client */
	mutex_lock(&nv_subdev(priv)->mutex);
	if (list_empty(&nv_engine(priv)->contexts)) {
		ret = nouveau_engctx_create(parent, engine, oclass, NULL,
					    0x10000, 0x10000,
					    NVOBJ_FLAG_HEAP, &ectx);
		*pobject = nv_object(ectx);
	}
	mutex_unlock(&nv_subdev(priv)->mutex);
	return ret;
}
Esempio n. 7
0
static int
nv10_fence_context_new(struct nouveau_channel *chan, int engine)
{
	struct nv10_fence_priv *priv = nv_engine(chan->dev, engine);
	struct nv10_fence_chan *fctx;
	struct nouveau_gpuobj *obj;
	int ret = 0;

	fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL);
	if (!fctx)
		return -ENOMEM;

	nouveau_fence_context_new(&fctx->base);

	if (priv->bo) {
		struct ttm_mem_reg *mem = &priv->bo->bo.mem;

		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_FROM_MEMORY,
					     mem->start * PAGE_SIZE, mem->size,
					     NV_MEM_ACCESS_RW,
					     NV_MEM_TARGET_VRAM, &obj);
		if (!ret) {
			ret = nouveau_ramht_insert(chan, NvSema, obj);
			nouveau_gpuobj_ref(NULL, &obj);
		}
	}

	if (ret)
		nv10_fence_context_del(chan, engine);
	return ret;
}
Esempio n. 8
0
static int
nv84_fence_context_new(struct nouveau_channel *chan, int engine)
{
	struct nv84_fence_priv *priv = nv_engine(chan->dev, engine);
	struct nv84_fence_chan *fctx;
	struct nouveau_gpuobj *obj;
	int ret;

	fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL);
	if (!fctx)
		return -ENOMEM;

	nouveau_fence_context_new(&fctx->base);

	ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_FROM_MEMORY,
				     priv->mem->vinst, priv->mem->size,
				     NV_MEM_ACCESS_RW,
				     NV_MEM_TARGET_VRAM, &obj);
	if (ret == 0) {
		ret = nouveau_ramht_insert(chan, NvSema, obj);
		nouveau_gpuobj_ref(NULL, &obj);
		nv_wo32(priv->mem, chan->id * 16, 0x00000000);
	}

	if (ret)
		nv84_fence_context_del(chan, engine);
	return ret;
}
Esempio n. 9
0
static int
nvc0_graph_construct_context(struct nouveau_channel *chan)
{
	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
	struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
	struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
	struct drm_device *dev = chan->dev;
	int ret, i;
	u32 *ctx;

	ctx = kmalloc(priv->grctx_size, GFP_KERNEL);
	if (!ctx)
		return -ENOMEM;

	if (!nouveau_ctxfw) {
		nv_wr32(dev, 0x409840, 0x80000000);
		nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
		nv_wr32(dev, 0x409504, 0x00000001);
		if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
			NV_ERROR(dev, "PGRAPH: HUB_SET_CHAN timeout\n");
			nvc0_graph_ctxctl_debug(dev);
			ret = -EBUSY;
			goto err;
		}
	} else {
Esempio n. 10
0
void
nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{
	struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
	int i;

	nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);

	nvc0_graph_mmio(priv, oclass->hub);
	nvc0_graph_mmio(priv, oclass->gpc);
	nvc0_graph_mmio(priv, oclass->zcull);
	nvc0_graph_mmio(priv, oclass->tpc);
	nvc0_graph_mmio(priv, oclass->ppc);

	nv_wr32(priv, 0x404154, 0x00000000);

	oclass->bundle(info);
	oclass->pagepool(info);
	oclass->attrib(info);
	oclass->unkn(priv);

	nvc0_grctx_generate_tpcid(priv);
	nvc0_grctx_generate_r406028(priv);
	nvc0_grctx_generate_r4060a8(priv);
	nve4_grctx_generate_r418bb8(priv);
	nvc0_grctx_generate_r406800(priv);

	for (i = 0; i < 8; i++)
		nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);

	nvc0_graph_icmd(priv, oclass->icmd);
	nv_wr32(priv, 0x404154, 0x00000400);
	nvc0_graph_mthd(priv, oclass->mthd);
	nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
}
Esempio n. 11
0
int
nouveau_parent_create_(struct nouveau_object *parent,
		       struct nouveau_object *engine,
		       struct nouveau_oclass *oclass, u32 pclass,
		       struct nouveau_oclass *sclass, u64 engcls,
		       int size, void **pobject)
{
	struct nouveau_parent *object;
	struct nouveau_sclass *nclass;
	int ret;

	ret = nouveau_object_create_(parent, engine, oclass, pclass |
				     NV_PARENT_CLASS, size, pobject);
	object = *pobject;
	if (ret)
		return ret;

	while (sclass && sclass->ofuncs) {
		nclass = kzalloc(sizeof(*nclass), GFP_KERNEL);
		if (!nclass)
			return -ENOMEM;

		nclass->sclass = object->sclass;
		object->sclass = nclass;
		nclass->engine = engine ? nv_engine(engine) : NULL;
		nclass->oclass = sclass;
		sclass++;
	}

	object->engine = engcls;
	return 0;
}
Esempio n. 12
0
static void
nv84_crypt_intr(struct nouveau_subdev *subdev)
{
	struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
	struct nouveau_engine *engine = nv_engine(subdev);
	struct nouveau_object *engctx;
	struct nv84_crypt_priv *priv = (void *)subdev;
	u32 stat = nv_rd32(priv, 0x102130);
	u32 mthd = nv_rd32(priv, 0x102190);
	u32 data = nv_rd32(priv, 0x102194);
	u32 inst = nv_rd32(priv, 0x102188) & 0x7fffffff;
	int chid;

	engctx = nouveau_engctx_get(engine, inst);
	chid   = pfifo->chid(pfifo, engctx);

	if (stat) {
		nv_error(priv, "%s", "");
		nouveau_bitfield_print(nv84_crypt_intr_mask, stat);
		pr_cont(" ch %d [0x%010llx %s] mthd 0x%04x data 0x%08x\n",
		       chid, (u64)inst << 12, nouveau_client_name(engctx),
		       mthd, data);
	}

	nv_wr32(priv, 0x102130, stat);
	nv_wr32(priv, 0x10200c, 0x10);

	nouveau_engctx_put(engctx);
}
Esempio n. 13
0
void
nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{
	struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
	int i;

	nv_mask(priv, 0x000260, 0x00000001, 0x00000000);

	for (i = 0; oclass->hub[i]; i++)
		nvc0_graph_mmio(priv, oclass->hub[i]);
	for (i = 0; oclass->gpc[i]; i++)
		nvc0_graph_mmio(priv, oclass->gpc[i]);

	nv_wr32(priv, 0x404154, 0x00000000);

	oclass->mods(priv, info);
	oclass->unkn(priv);

	nvc0_grctx_generate_tpcid(priv);
	nvc0_grctx_generate_r406028(priv);
	nvc0_grctx_generate_r4060a8(priv);
	nve4_grctx_generate_r418bb8(priv);
	nvc0_grctx_generate_r406800(priv);

	for (i = 0; i < 8; i++)
		nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);

	nvc0_graph_icmd(priv, oclass->icmd);
	nv_wr32(priv, 0x404154, 0x00000400);
	nvc0_graph_mthd(priv, oclass->mthd);
	nv_mask(priv, 0x000260, 0x00000001, 0x00000001);
}
Esempio n. 14
0
int
nv84_fence_create(struct drm_device *dev)
{
	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nv84_fence_priv *priv;
	int ret;

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->base.engine.destroy = nv84_fence_destroy;
	priv->base.engine.init = nv84_fence_init;
	priv->base.engine.fini = nv84_fence_fini;
	priv->base.engine.context_new = nv84_fence_context_new;
	priv->base.engine.context_del = nv84_fence_context_del;
	priv->base.emit = nv84_fence_emit;
	priv->base.sync = nv84_fence_sync;
	priv->base.read = nv84_fence_read;
	dev_priv->eng[NVOBJ_ENGINE_FENCE] = &priv->base.engine;

	ret = nouveau_gpuobj_new(dev, NULL, 16 * pfifo->channels,
				 0x1000, 0, &priv->mem);
	if (ret)
		goto out;

out:
	if (ret)
		nv84_fence_destroy(dev, NVOBJ_ENGINE_FENCE);
	return ret;
}
Esempio n. 15
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static int
gk110_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
	      struct nvkm_oclass *oclass, void *data, u32 size,
	      struct nvkm_object **pobject)
{
	struct gf100_pm_priv *priv;
	int ret;

	ret = nvkm_pm_create(parent, engine, oclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	nv_engine(priv)->cclass = &nvkm_pm_cclass;
	nv_engine(priv)->sclass =  nvkm_pm_sclass;
	return 0;
}
Esempio n. 16
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static void
nv98_ppp_destroy(struct drm_device *dev, int engine)
{
	struct nv98_ppp_engine *pppp = nv_engine(dev, engine);

	NVOBJ_ENGINE_DEL(dev, PPP);

	kfree(pppp);
}
static void
nv98_crypt_destroy(struct drm_device *dev, int engine)
{
	struct nv98_crypt_engine *pcrypt = nv_engine(dev, engine);

	NVOBJ_ENGINE_DEL(dev, CRYPT);

	kfree(pcrypt);
}
Esempio n. 18
0
File: nv04.c Progetto: 168519/linux
static int
nv04_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
	     struct nvkm_oclass *oclass, void *data, u32 size,
	     struct nvkm_object **pobject)
{
	struct nv04_sw_priv *priv;
	int ret;

	ret = nvkm_sw_create(parent, engine, oclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	nv_engine(priv)->cclass = &nv04_sw_cclass;
	nv_engine(priv)->sclass = nv04_sw_sclass;
	nv_subdev(priv)->intr = nv04_sw_intr;
	return 0;
}
Esempio n. 19
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static void
nv84_bsp_destroy(struct drm_device *dev, int engine)
{
	struct nv84_bsp_engine *pbsp = nv_engine(dev, engine);

	NVOBJ_ENGINE_DEL(dev, BSP);

	kfree(pbsp);
}
Esempio n. 20
0
static void
nv84_fence_destroy(struct drm_device *dev, int engine)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nv84_fence_priv *priv = nv_engine(dev, engine);

	nouveau_gpuobj_ref(NULL, &priv->mem);
	dev_priv->eng[engine] = NULL;
	kfree(priv);
}
Esempio n. 21
0
File: nv50.c Progetto: 168519/linux
static int
nv50_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
	       struct nvkm_oclass *oclass, void *data, u32 size,
	       struct nvkm_object **pobject)
{
	struct nv50_mpeg_priv *priv;
	int ret;

	ret = nvkm_mpeg_create(parent, engine, oclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	nv_subdev(priv)->unit = 0x00400002;
	nv_subdev(priv)->intr = nv50_vpe_intr;
	nv_engine(priv)->cclass = &nv50_mpeg_cclass;
	nv_engine(priv)->sclass = nv50_mpeg_sclass;
	return 0;
}
int
nv50_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
		   struct nouveau_oclass *oclass, void *data, u32 size,
		   struct nouveau_object **pobject)
{
	struct nv50_software_oclass *pclass = (void *)oclass;
	struct nv50_software_priv *priv;
	int ret;

	ret = nouveau_software_create(parent, engine, oclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	nv_engine(priv)->cclass = pclass->cclass;
	nv_engine(priv)->sclass = pclass->sclass;
	nv_subdev(priv)->intr = nv04_software_intr;
	return 0;
}
Esempio n. 23
0
File: g84.c Progetto: 168519/linux
static int
g84_cipher_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
		struct nvkm_oclass *oclass, void *data, u32 size,
		struct nvkm_object **pobject)
{
	struct g84_cipher_priv *priv;
	int ret;

	ret = nvkm_engine_create(parent, engine, oclass, true,
				 "PCIPHER", "cipher", &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	nv_subdev(priv)->unit = 0x00004000;
	nv_subdev(priv)->intr = g84_cipher_intr;
	nv_engine(priv)->cclass = &g84_cipher_cclass;
	nv_engine(priv)->sclass = g84_cipher_sclass;
	return 0;
}
Esempio n. 24
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static int
nv84_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	       struct nouveau_oclass *oclass, void *data, u32 size,
	       struct nouveau_object **pobject)
{
	struct nv84_crypt_priv *priv;
	int ret;

	ret = nouveau_engine_create(parent, engine, oclass, true,
				    "PCRYPT", "crypt", &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	nv_subdev(priv)->unit = 0x00004000;
	nv_subdev(priv)->intr = nv84_crypt_intr;
	nv_engine(priv)->cclass = &nv84_crypt_cclass;
	nv_engine(priv)->sclass = nv84_crypt_sclass;
	return 0;
}
Esempio n. 25
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static int
nvc0_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
		   struct nouveau_oclass *oclass, void *data, u32 size,
		   struct nouveau_object **pobject)
{
	struct nvc0_software_priv *priv;
	int ret;

	nv_warn(parent, "[%s]\n", __PRETTY_FUNCTION__);

	ret = nouveau_software_create(parent, engine, oclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	nv_engine(priv)->cclass = &nvc0_software_cclass;
	nv_engine(priv)->sclass = nvc0_software_sclass;
	nv_subdev(priv)->intr = nv04_software_intr;
	return 0;
}
Esempio n. 26
0
static int
nv84_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	     struct nouveau_oclass *oclass, void *data, u32 size,
	     struct nouveau_object **pobject)
{
	struct nouveau_xtensa *priv;
	int ret;

	ret = nouveau_xtensa_create(parent, engine, oclass, 0xf000, true,
				    "PVP", "vp", &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	nv_subdev(priv)->unit = 0x01020000;
	nv_engine(priv)->cclass = &nv84_vp_cclass;
	nv_engine(priv)->sclass = nv84_vp_sclass;
	priv->fifo_val = 0x111;
	priv->unkd28 = 0x9c544;
	return 0;
}
Esempio n. 27
0
static int
nvc0_graph_set_shader_exceptions(struct nouveau_object *object, u32 mthd,
				 void *pdata, u32 size)
{
	struct nvc0_graph_priv *priv = (void *)nv_engine(object);
	if (size >= sizeof(u32)) {
		u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000;
		nv_wr32(priv, 0x419e44, data);
		nv_wr32(priv, 0x419e4c, data);
		return 0;
	}
	return -EINVAL;
}
Esempio n. 28
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static int
nvf0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
		  struct nouveau_oclass *oclass, void *data, u32 size,
		  struct nouveau_object **pobject)
{
	struct nvc0_perfmon_priv *priv;
	int ret;

	ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
				   nve0_perfmon_pwr);
	if (ret)
		return ret;

	nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
	nv_engine(priv)->sclass =  nouveau_perfmon_sclass;
	return 0;
}
Esempio n. 29
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static int
nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	       struct nouveau_oclass *oclass, void *data, u32 size,
	       struct nouveau_object **pobject)
{
	struct nv50_disp_priv *priv;
	int ret;

	ret = nouveau_disp_create(parent, engine, oclass, "PDISP",
				  "display", &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	nv_engine(priv)->sclass = nve0_disp_base_oclass;
	nv_engine(priv)->cclass = &nv50_disp_cclass;
	nv_subdev(priv)->intr = nvd0_disp_intr;
	priv->sclass = nve0_disp_sclass;
	priv->head.nr = nv_rd32(priv, 0x022448);
	priv->dac.nr = 3;
	priv->sor.nr = 4;
	priv->dac.power = nv50_dac_power;
	priv->dac.sense = nv50_dac_sense;
	priv->sor.power = nv50_sor_power;
	priv->sor.hda_eld = nvd0_hda_eld;
	priv->sor.hdmi = nvd0_hdmi_ctrl;
	priv->sor.dp_train = nvd0_sor_dp_train;
	priv->sor.dp_train_init = nv94_sor_dp_train_init;
	priv->sor.dp_train_fini = nv94_sor_dp_train_fini;
	priv->sor.dp_lnkctl = nvd0_sor_dp_lnkctl;
	priv->sor.dp_drvctl = nvd0_sor_dp_drvctl;

	INIT_LIST_HEAD(&priv->base.vblank.list);
	spin_lock_init(&priv->base.vblank.lock);
	return 0;
}
Esempio n. 30
0
static void
gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{
	struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
	int i;

	nvc0_graph_mmio(priv, oclass->hub);
	nvc0_graph_mmio(priv, oclass->gpc);
	nvc0_graph_mmio(priv, oclass->zcull);
	nvc0_graph_mmio(priv, oclass->tpc);
	nvc0_graph_mmio(priv, oclass->ppc);

	nv_wr32(priv, 0x404154, 0x00000000);

	oclass->bundle(info);
	oclass->pagepool(info);
	oclass->attrib(info);
	oclass->unkn(priv);

	gm107_grctx_generate_tpcid(priv);
	nvc0_grctx_generate_r406028(priv);
	nve4_grctx_generate_r418bb8(priv);
	nvc0_grctx_generate_r406800(priv);

	nv_wr32(priv, 0x4064d0, 0x00000001);
	for (i = 1; i < 8; i++)
		nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
	nv_wr32(priv, 0x406500, 0x00000001);

	nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);

	if (priv->gpc_nr == 1) {
		nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]);
		nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]);
	} else {
		nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr);
		nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
	}

	nvc0_graph_icmd(priv, oclass->icmd);
	nv_wr32(priv, 0x404154, 0x00000400);
	nvc0_graph_mthd(priv, oclass->mthd);

	nv_mask(priv, 0x419e00, 0x00808080, 0x00808080);
	nv_mask(priv, 0x419ccc, 0x80000000, 0x80000000);
	nv_mask(priv, 0x419f80, 0x80000000, 0x80000000);
	nv_mask(priv, 0x419f88, 0x80000000, 0x80000000);
}