static int nvhost_scale3d_target(struct device *d, unsigned long *freq,
u32 flags)
{
long hz;
long after;
/* Inform that the clock is disabled */
if (!tegra_is_clk_enabled(power_profile.clk_3d)) {
*freq = 0;
return 0;
}
/* Limit the frequency */
if (*freq < power_profile.min_rate_3d)
*freq = power_profile.min_rate_3d;
else if (*freq > power_profile.max_rate_3d)
*freq = power_profile.max_rate_3d;
/* Check if we're already running at the desired speed */
if (*freq == clk_get_rate(power_profile.clk_3d))
return 0;
/* Set GPU clockrate */
if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA3)
nvhost_module_set_devfreq_rate(power_profile.dev,
clk_to_idx(power_profile.clk_3d2), 0);
nvhost_module_set_devfreq_rate(power_profile.dev,
clk_to_idx(power_profile.clk_3d), *freq);
/* Set EMC clockrate */
after = (long) clk_get_rate(power_profile.clk_3d);
after = INT_TO_FX(HZ_TO_MHZ(after));
hz = FXMUL(after, power_profile.emc_slope) +
power_profile.emc_offset;
hz -= FXMUL(power_profile.emc_dip_slope,
FXMUL(after - power_profile.emc_xmid,
after - power_profile.emc_xmid)) +
power_profile.emc_dip_offset;
hz = MHZ_TO_HZ(FX_TO_INT(hz + FX_HALF)); /* round to nearest */
hz = (hz < 0) ? 0 : hz;
nvhost_module_set_devfreq_rate(power_profile.dev,
clk_to_idx(power_profile.clk_3d_emc), hz);
/* Get the new clockrate */
*freq = clk_get_rate(power_profile.clk_3d);
return 0;
}
void nvhost_scale3d_callback(struct nvhost_device_profile *profile,
unsigned long freq)
{
struct nvhost_gr3d_params *gr3d_params = profile->private_data;
struct nvhost_emc_params *emc_params = &gr3d_params->emc_params;
long hz;
long after;
/* Set EMC clockrate */
after = (long) clk_get_rate(clk(profile, gr3d_params->clk_3d));
hz = nvhost_scale3d_get_emc_rate(emc_params, after);
nvhost_module_set_devfreq_rate(profile->pdev, gr3d_params->clk_3d_emc,
hz);
}
void nvhost_scale3d_callback(struct nvhost_device_profile *profile,
unsigned long freq)
{
struct nvhost_gr3d_params *gr3d_params = profile->private_data;
struct nvhost_device_data *pdata = platform_get_drvdata(profile->pdev);
struct nvhost_emc_params *emc_params = &gr3d_params->emc_params;
long hz;
long after;
/* Set EMC clockrate */
after = (long) clk_get_rate(clk(profile, gr3d_params->clk_3d));
hz = nvhost_scale3d_get_emc_rate(emc_params, after);
nvhost_module_set_devfreq_rate(profile->pdev, gr3d_params->clk_3d_emc,
hz);
if (pdata->gpu_edp_device) {
u32 avg = 0;
actmon_op().read_avg_norm(profile->actmon, &avg);
tegra_edp_notify_gpu_load(avg);
}
}
static int nvhost_scale_target(struct device *dev, unsigned long *freq,
u32 flags)
{
struct nvhost_device_data *pdata = dev_get_drvdata(dev);
struct nvhost_device_profile *profile = pdata->power_profile;
if (!tegra_is_clk_enabled(profile->clk)) {
*freq = profile->devfreq_profile.freq_table[0];
return 0;
}
*freq = clk_round_rate(clk_get_parent(profile->clk), *freq);
if (clk_get_rate(profile->clk) == *freq)
return 0;
nvhost_module_set_devfreq_rate(profile->pdev, 0, *freq);
if (pdata->scaling_post_cb)
pdata->scaling_post_cb(profile, *freq);
*freq = clk_get_rate(profile->clk);
return 0;
}
