static void init_cpus(const char *cpu_model, const char *privdev, hwaddr periphbase, qemu_irq *pic, bool secure) { ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); DeviceState *dev; SysBusDevice *busdev; int n; if (!cpu_oc) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } /* Create the actual CPUs */ for (n = 0; n < smp_cpus; n++) { Object *cpuobj = object_new(object_class_get_name(cpu_oc)); Error *err = NULL; if (!secure) { object_property_set_bool(cpuobj, false, "has_el3", NULL); } if (object_property_find(cpuobj, "reset-cbar", NULL)) { object_property_set_int(cpuobj, periphbase, "reset-cbar", &error_abort); } object_property_set_bool(cpuobj, true, "realized", &err); if (err) { error_report_err(err); exit(1); } } /* Create the private peripheral devices (including the GIC); * this must happen after the CPUs are created because a15mpcore_priv * wires itself up to the CPU's generic_timer gpio out lines. */ dev = qdev_create(NULL, privdev); qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); qdev_init_nofail(dev); busdev = SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, periphbase); /* Interrupts [42:0] are from the motherboard; * [47:43] are reserved; [63:48] are daughterboard * peripherals. Note that some documentation numbers * external interrupts starting from 32 (because there * are internal interrupts 0..31). */ for (n = 0; n < 64; n++) { pic[n] = qdev_get_gpio_in(dev, n); } /* Connect the CPUs to the GIC */ for (n = 0; n < smp_cpus; n++) { DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); } }
static void microbit_init(MachineState *machine) { MicrobitMachineState *s = MICROBIT_MACHINE(machine); MemoryRegion *system_memory = get_system_memory(); MemoryRegion *mr; Object *soc = OBJECT(&s->nrf51); Object *i2c = OBJECT(&s->i2c); sysbus_init_child_obj(OBJECT(machine), "nrf51", soc, sizeof(s->nrf51), TYPE_NRF51_SOC); qdev_prop_set_chr(DEVICE(&s->nrf51), "serial0", serial_hd(0)); object_property_set_link(soc, OBJECT(system_memory), "memory", &error_fatal); object_property_set_bool(soc, true, "realized", &error_fatal); /* * Overlap the TWI stub device into the SoC. This is a microbit-specific * hack until we implement the nRF51 TWI controller properly and the * magnetometer/accelerometer devices. */ sysbus_init_child_obj(OBJECT(machine), "microbit.twi", i2c, sizeof(s->i2c), TYPE_MICROBIT_I2C); object_property_set_bool(i2c, true, "realized", &error_fatal); mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(i2c), 0); memory_region_add_subregion_overlap(&s->nrf51.container, NRF51_TWI_BASE, mr, -1); armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, NRF51_SOC(soc)->flash_size); }
static void bcm2835_realize(DeviceState *dev, Error **errp) { BCM2835State *s = BCM2835(dev); Error *err = NULL; /* common peripherals from bcm2835 */ object_property_set_bool(OBJECT(&s->peripherals), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0, BCM2835_PERI_BASE, 1); object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); if (err) { error_report_err(err); exit(1); } sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); }
static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size) { PL080State *dma = opaque; int i = dma - &mms->dma[0]; SysBusDevice *s; char *mscname = g_strdup_printf("%s-msc", name); TZMSC *msc = &mms->msc[i]; DeviceState *iotkitdev = DEVICE(&mms->iotkit); MemoryRegion *msc_upstream; MemoryRegion *msc_downstream; /* * Each DMA device is a PL081 whose transaction master interface * is guarded by a Master Security Controller. The downstream end of * the MSC connects to the IoTKit AHB Slave Expansion port, so the * DMA devices can see all devices and memory that the CPU does. */ sysbus_init_child_obj(OBJECT(mms), mscname, msc, sizeof(*msc), TYPE_TZ_MSC); msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0); object_property_set_link(OBJECT(msc), OBJECT(msc_downstream), "downstream", &error_fatal); object_property_set_link(OBJECT(msc), OBJECT(mms), "idau", &error_fatal); object_property_set_bool(OBJECT(msc), true, "realized", &error_fatal); qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0, qdev_get_gpio_in_named(iotkitdev, "mscexp_status", i)); qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i, qdev_get_gpio_in_named(DEVICE(msc), "irq_clear", 0)); qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i, qdev_get_gpio_in_named(DEVICE(msc), "cfg_nonsec", 0)); qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter), ARRAY_SIZE(mms->ppc) + i, qdev_get_gpio_in_named(DEVICE(msc), "cfg_sec_resp", 0)); msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0); sysbus_init_child_obj(OBJECT(mms), name, dma, sizeof(*dma), TYPE_PL081); object_property_set_link(OBJECT(dma), OBJECT(msc_upstream), "downstream", &error_fatal); object_property_set_bool(OBJECT(dma), true, "realized", &error_fatal); s = SYS_BUS_DEVICE(dma); /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 58 + i * 3)); sysbus_connect_irq(s, 1, get_sse_irq_in(mms, 56 + i * 3)); sysbus_connect_irq(s, 2, get_sse_irq_in(mms, 57 + i * 3)); g_free(mscname); return sysbus_mmio_get_region(s, 0); }
static void xlnx_zynqmp_pmu_init(MachineState *machine) { XlnxZynqMPPMUSoCState *pmu = g_new0(XlnxZynqMPPMUSoCState, 1); MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *pmu_rom = g_new(MemoryRegion, 1); MemoryRegion *pmu_ram = g_new(MemoryRegion, 1); XlnxZynqMPIPI *ipi[XLNX_ZYNQMP_PMU_NUM_IPIS]; qemu_irq irq[32]; int i; /* Create the ROM */ memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom", XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal); memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR, pmu_rom); /* Create the RAM */ memory_region_init_ram(pmu_ram, NULL, "xlnx-zynqmp-pmu.ram", machine->ram_size, &error_fatal); memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR, pmu_ram); /* Create the PMU device */ object_initialize(pmu, sizeof(XlnxZynqMPPMUSoCState), TYPE_XLNX_ZYNQMP_PMU_SOC); object_property_add_child(OBJECT(machine), "pmu", OBJECT(pmu), &error_abort); object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal); for (i = 0; i < 32; i++) { irq[i] = qdev_get_gpio_in(DEVICE(&pmu->intc), i); } /* Create and connect the IPI device */ for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) { ipi[i] = g_new0(XlnxZynqMPIPI, 1); object_initialize(ipi[i], sizeof(XlnxZynqMPIPI), TYPE_XLNX_ZYNQMP_IPI); qdev_set_parent_bus(DEVICE(ipi[i]), sysbus_get_default()); } for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) { object_property_set_bool(OBJECT(ipi[i]), true, "realized", &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(ipi[i]), 0, ipi_addr[i]); sysbus_connect_irq(SYS_BUS_DEVICE(ipi[i]), 0, irq[ipi_irq[i]]); } /* Load the kernel */ microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR, machine->ram_size, machine->initrd_filename, machine->dtb, NULL); }
static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size) { CMSDKAPBUART *uart = opaque; int i = uart - &mms->uart[0]; int rxirqno = i * 2; int txirqno = i * 2 + 1; int combirqno = i + 10; SysBusDevice *s; DeviceState *iotkitdev = DEVICE(&mms->iotkit); DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]), TYPE_CMSDK_APB_UART); qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal); s = SYS_BUS_DEVICE(uart); sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", txirqno)); sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", rxirqno)); sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); sysbus_connect_irq(s, 4, qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", combirqno)); return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); }
static void spapr_cpu_core_realize_child(Object *child, sPAPRMachineState *spapr, Error **errp) { Error *local_err = NULL; CPUState *cs = CPU(child); PowerPCCPU *cpu = POWERPC_CPU(cs); object_property_set_bool(child, true, "realized", &local_err); if (local_err) { goto error; } spapr_cpu_init(spapr, cpu, &local_err); if (local_err) { goto error; } cpu->intc = icp_create(child, spapr->icp_type, XICS_FABRIC(spapr), &local_err); if (local_err) { goto error; } return; error: error_propagate(errp, local_err); }
static void s390_skeys_instance_init(Object *obj) { object_property_add_bool(obj, "migration-enabled", s390_skeys_get_migration_enabled, s390_skeys_set_migration_enabled, NULL); object_property_set_bool(obj, true, "migration-enabled", NULL); }
/* VGA device wrapper around PCI device around virtio GPU */ static void virtio_vga_realize(VirtIOPCIProxy *vpci_dev, Error **errp) { VirtIOVGA *vvga = VIRTIO_VGA(vpci_dev); VirtIOGPU *g = &vvga->vdev; VGACommonState *vga = &vvga->vga; Error *err = NULL; uint32_t offset; int i; /* init vga compat bits */ vga->vram_size_mb = 8; vga_common_init(vga, OBJECT(vpci_dev), false); vga_init(vga, OBJECT(vpci_dev), pci_address_space(&vpci_dev->pci_dev), pci_address_space_io(&vpci_dev->pci_dev), true); pci_register_bar(&vpci_dev->pci_dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram); /* * Configure virtio bar and regions * * We use bar #2 for the mmio regions, to be compatible with stdvga. * virtio regions are moved to the end of bar #2, to make room for * the stdvga mmio registers at the start of bar #2. */ vpci_dev->modern_mem_bar = 2; vpci_dev->msix_bar = 4; offset = memory_region_size(&vpci_dev->modern_bar); offset -= vpci_dev->notify.size; vpci_dev->notify.offset = offset; offset -= vpci_dev->device.size; vpci_dev->device.offset = offset; offset -= vpci_dev->isr.size; vpci_dev->isr.offset = offset; offset -= vpci_dev->common.size; vpci_dev->common.offset = offset; /* init virtio bits */ qdev_set_parent_bus(DEVICE(g), BUS(&vpci_dev->bus)); /* force virtio-1.0 */ vpci_dev->flags &= ~VIRTIO_PCI_FLAG_DISABLE_MODERN; vpci_dev->flags |= VIRTIO_PCI_FLAG_DISABLE_LEGACY; object_property_set_bool(OBJECT(g), true, "realized", &err); if (err) { error_propagate(errp, err); return; } /* add stdvga mmio regions */ pci_std_vga_mmio_region_init(vga, &vpci_dev->modern_bar, vvga->vga_mrs, true); vga->con = g->scanout[0].con; graphic_console_set_hwops(vga->con, &virtio_vga_ops, vvga); for (i = 0; i < g->conf.max_outputs; i++) { object_property_set_link(OBJECT(g->scanout[i].con), OBJECT(vpci_dev), "device", errp); } }
PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem, hwaddr base, BlockBackend *blk, qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) { DeviceState *dev, *carddev; SysBusDevice *sbd; PXA2xxMMCIState *s; Error *err = NULL; dev = qdev_create(NULL, TYPE_PXA2XX_MMCI); s = PXA2XX_MMCI(dev); sbd = SYS_BUS_DEVICE(dev); sysbus_mmio_map(sbd, 0, base); sysbus_connect_irq(sbd, 0, irq); qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma); qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma); /* Create and plug in the sd card */ carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); qdev_prop_set_drive(carddev, "drive", blk, &err); if (err) { error_report("failed to init SD card: %s", error_get_pretty(err)); return NULL; } object_property_set_bool(OBJECT(carddev), true, "realized", &err); if (err) { error_report("failed to init SD card: %s", error_get_pretty(err)); return NULL; } return s; }
static void virtio_gpu_pci_base_realize(VirtIOPCIProxy *vpci_dev, Error **errp) { VirtIOGPUPCIBase *vgpu = VIRTIO_GPU_PCI_BASE(vpci_dev); VirtIOGPUBase *g = vgpu->vgpu; DeviceState *vdev = DEVICE(g); int i; Error *local_error = NULL; qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus)); if (!virtio_pci_force_virtio_1(vpci_dev, errp)) { return; } object_property_set_bool(OBJECT(vdev), true, "realized", &local_error); if (local_error) { error_propagate(errp, local_error); return; } for (i = 0; i < g->conf.max_outputs; i++) { object_property_set_link(OBJECT(g->scanout[i].con), OBJECT(vpci_dev), "device", errp); } }
static ICSState *spapr_ics_create(sPAPRMachineState *spapr, const char *type_ics, int nr_irqs, Error **errp) { Error *local_err = NULL; Object *obj; obj = object_new(type_ics); object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), &error_abort); object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); if (local_err) { goto error; } object_property_set_bool(obj, true, "realized", &local_err); if (local_err) { goto error; } return ICS_BASE(obj); error: error_propagate(errp, local_err); return NULL; }
static void virtio_serial_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) { VirtIOSerialPCI *dev = VIRTIO_SERIAL_PCI(vpci_dev); DeviceState *vdev = DEVICE(&dev->vdev); DeviceState *proxy = DEVICE(vpci_dev); char *bus_name; if (vpci_dev->class_code != PCI_CLASS_COMMUNICATION_OTHER && vpci_dev->class_code != PCI_CLASS_DISPLAY_OTHER && /* qemu 0.10 */ vpci_dev->class_code != PCI_CLASS_OTHERS) { /* qemu-kvm */ vpci_dev->class_code = PCI_CLASS_COMMUNICATION_OTHER; } /* backwards-compatibility with machines that were created with DEV_NVECTORS_UNSPECIFIED */ if (vpci_dev->nvectors == DEV_NVECTORS_UNSPECIFIED) { vpci_dev->nvectors = dev->vdev.serial.max_virtserial_ports + 1; } /* * For command line compatibility, this sets the virtio-serial-device bus * name as before. */ if (proxy->id) { bus_name = g_strdup_printf("%s.0", proxy->id); virtio_device_set_child_bus_name(VIRTIO_DEVICE(vdev), bus_name); g_free(bus_name); } qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus)); object_property_set_bool(OBJECT(vdev), true, "realized", errp); }
static int vmstate_cpuhp_pre_load(void *opaque) { ICH9LPCPMRegs *s = opaque; Object *obj = OBJECT(s->gpe_cpu.device); object_property_set_bool(obj, false, "cpu-hotplug-legacy", &error_abort); return 0; }
XtensaCPU *cpu_xtensa_init(const char *cpu_model) { XtensaCPU *cpu; CPUXtensaState *env; const XtensaConfig *config = NULL; XtensaConfigList *core = xtensa_cores; for (; core; core = core->next) if (strcmp(core->config->name, cpu_model) == 0) { config = core->config; break; } if (config == NULL) { return NULL; } cpu = XTENSA_CPU(object_new(TYPE_XTENSA_CPU)); env = &cpu->env; env->config = config; xtensa_irq_init(env); object_property_set_bool(OBJECT(cpu), true, "realized", NULL); return cpu; }
static void raven_pcihost_realizefn(DeviceState *d, Error **errp) { SysBusDevice *dev = SYS_BUS_DEVICE(d); PCIHostState *h = PCI_HOST_BRIDGE(dev); PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev); MemoryRegion *address_space_mem = get_system_memory(); int i; for (i = 0; i < 4; i++) { sysbus_init_irq(dev, &s->irq[i]); } pci_bus_irqs(&s->pci_bus, prep_set_irq, prep_map_irq, s->irq, 4); memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, s, "pci-conf-idx", 1); sysbus_add_io(dev, 0xcf8, &h->conf_mem); sysbus_init_ioports(&h->busdev, 0xcf8, 1); memory_region_init_io(&h->data_mem, &pci_host_data_be_ops, s, "pci-conf-data", 1); sysbus_add_io(dev, 0xcfc, &h->data_mem); sysbus_init_ioports(&h->busdev, 0xcfc, 1); memory_region_init_io(&h->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000); memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg); memory_region_init_io(&s->intack, &PPC_intack_ops, s, "pci-intack", 1); memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->intack); /* TODO Remove once realize propagates to child devices. */ object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp); }
static void mpcore_priv_realize(DeviceState *dev, Error **errp) { SysBusDevice *sbd = SYS_BUS_DEVICE(dev); ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev); DeviceState *scudev = DEVICE(&s->scu); DeviceState *gicdev = DEVICE(&s->gic); DeviceState *mptimerdev = DEVICE(&s->mptimer); DeviceState *wdtimerdev = DEVICE(&s->wdtimer); Error *err = NULL; qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); return; } qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); return; } /* Pass through outbound IRQ lines from the GIC */ sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic)); /* Pass through inbound GPIO lines to the GIC */ qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32); qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); return; } qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu); object_property_set_bool(OBJECT(&s->wdtimer), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); return; } mpcore_priv_map_setup(s); }
static void macio_oldworld_realize(PCIDevice *d, Error **errp) { MacIOState *s = MACIO(d); OldWorldMacIOState *os = OLDWORLD_MACIO(d); DeviceState *pic_dev = DEVICE(os->pic); Error *err = NULL; SysBusDevice *sysbus_dev; macio_common_realize(d, &err); if (err) { error_propagate(errp, err); return; } sysbus_dev = SYS_BUS_DEVICE(&s->cuda); sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev, OLDWORLD_CUDA_IRQ)); sysbus_dev = SYS_BUS_DEVICE(&s->escc); sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev, OLDWORLD_ESCCB_IRQ)); sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev, OLDWORLD_ESCCA_IRQ)); object_property_set_bool(OBJECT(&os->nvram), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_dev = SYS_BUS_DEVICE(&os->nvram); memory_region_add_subregion(&s->bar, 0x60000, sysbus_mmio_get_region(sysbus_dev, 0)); pmac_format_nvram_partition(&os->nvram, os->nvram.size); /* Heathrow PIC */ sysbus_dev = SYS_BUS_DEVICE(os->pic); memory_region_add_subregion(&s->bar, 0x0, sysbus_mmio_get_region(sysbus_dev, 0)); /* IDE buses */ macio_realize_ide(s, &os->ide[0], qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_IRQ), qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_DMA_IRQ), 0x16, &err); if (err) { error_propagate(errp, err); return; } macio_realize_ide(s, &os->ide[1], qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_IRQ), qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_DMA_IRQ), 0x1a, &err); if (err) { error_propagate(errp, err); return; } }
static inline void s390_machine_initfn(Object *obj) { object_property_add_bool(obj, "aes-key-wrap", machine_get_aes_key_wrap, machine_set_aes_key_wrap, NULL); object_property_set_description(obj, "aes-key-wrap", "enable/disable AES key wrapping using the CPACF wrapping key", NULL); object_property_set_bool(obj, true, "aes-key-wrap", NULL); object_property_add_bool(obj, "dea-key-wrap", machine_get_dea_key_wrap, machine_set_dea_key_wrap, NULL); object_property_set_description(obj, "dea-key-wrap", "enable/disable DEA key wrapping using the CPACF wrapping key", NULL); object_property_set_bool(obj, true, "dea-key-wrap", NULL); }
TileGXCPU *cpu_tilegx_init(const char *cpu_model) { TileGXCPU *cpu; cpu = TILEGX_CPU(object_new(TYPE_TILEGX_CPU)); object_property_set_bool(OBJECT(cpu), true, "realized", NULL); return cpu; }
static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size) { MPS2FPGAIO *fpgaio = opaque; object_initialize(fpgaio, sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO); qdev_set_parent_bus(DEVICE(fpgaio), sysbus_get_default()); object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); }
S390CPU *cpu_s390x_init(const char *cpu_model) { S390CPU *cpu; cpu = S390_CPU(object_new(TYPE_S390_CPU)); object_property_set_bool(OBJECT(cpu), true, "realized", NULL); return cpu; }
static void macio_common_realize(PCIDevice *d, Error **errp) { MacIOState *s = MACIO(d); SysBusDevice *sysbus_dev; Error *err = NULL; object_property_set_bool(OBJECT(&s->dbdma), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_dev = SYS_BUS_DEVICE(&s->dbdma); memory_region_add_subregion(&s->bar, 0x08000, sysbus_mmio_get_region(sysbus_dev, 0)); qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency", s->frequency); object_property_set_bool(OBJECT(&s->cuda), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_dev = SYS_BUS_DEVICE(&s->cuda); memory_region_add_subregion(&s->bar, 0x16000, sysbus_mmio_get_region(sysbus_dev, 0)); qdev_prop_set_uint32(DEVICE(&s->escc), "disabled", 0); qdev_prop_set_uint32(DEVICE(&s->escc), "frequency", ESCC_CLOCK); qdev_prop_set_uint32(DEVICE(&s->escc), "it_shift", 4); qdev_prop_set_chr(DEVICE(&s->escc), "chrA", serial_hd(0)); qdev_prop_set_chr(DEVICE(&s->escc), "chrB", serial_hd(1)); qdev_prop_set_uint32(DEVICE(&s->escc), "chnBtype", escc_serial); qdev_prop_set_uint32(DEVICE(&s->escc), "chnAtype", escc_serial); object_property_set_bool(OBJECT(&s->escc), true, "realized", &err); if (err) { error_propagate(errp, err); return; } macio_bar_setup(s); pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar); }
static void netduino2_init(MachineState *machine) { DeviceState *dev; dev = qdev_create(NULL, TYPE_STM32F205_SOC); if (machine->kernel_filename) { qdev_prop_set_string(dev, "kernel-filename", machine->kernel_filename); } qdev_prop_set_string(dev, "cpu-model", "cortex-m3"); object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal); }
static void macio_realize_ide(MacIOState *s, MACIOIDEState *ide, qemu_irq irq0, qemu_irq irq1, int dmaid, Error **errp) { SysBusDevice *sysbus_dev; sysbus_dev = SYS_BUS_DEVICE(ide); sysbus_connect_irq(sysbus_dev, 0, irq0); sysbus_connect_irq(sysbus_dev, 1, irq1); macio_ide_register_dma(ide, s->dbdma, dmaid); object_property_set_bool(OBJECT(ide), true, "realized", errp); }
static void digic_realize(DeviceState *dev, Error **errp) { DigicState *s = DIGIC(dev); Error *err = NULL; SysBusDevice *sbd; int i; object_property_set_bool(OBJECT(&s->cpu), true, "reset-hivecs", &err); if (err != NULL) { error_propagate(errp, err); return; } object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); return; } for (i = 0; i < DIGIC4_NB_TIMERS; i++) { object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); return; } sbd = SYS_BUS_DEVICE(&s->timer[i]); sysbus_mmio_map(sbd, 0, DIGIC4_TIMER_BASE(i)); } qdev_prop_set_chr(DEVICE(&s->uart), "chardev", serial_hds[0]); object_property_set_bool(OBJECT(&s->uart), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); return; } sbd = SYS_BUS_DEVICE(&s->uart); sysbus_mmio_map(sbd, 0, DIGIC_UART_BASE); }
static void vhost_scsi_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) { VHostSCSIPCI *dev = VHOST_SCSI_PCI(vpci_dev); DeviceState *vdev = DEVICE(&dev->vdev); VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(vdev); if (vpci_dev->nvectors == DEV_NVECTORS_UNSPECIFIED) { vpci_dev->nvectors = vs->conf.num_queues + 3; } qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus)); object_property_set_bool(OBJECT(vdev), true, "realized", errp); }
static void xics_realize(DeviceState *dev, Error **errp) { XICSState *icp = XICS(dev); Error *error = NULL; int i; if (!icp->nr_servers) { error_setg(errp, "Number of servers needs to be greater 0"); return; } /* Registration of global state belongs into realize */ spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive); spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive); spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off); spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on); spapr_register_hypercall(H_CPPR, h_cppr); spapr_register_hypercall(H_IPI, h_ipi); spapr_register_hypercall(H_XIRR, h_xirr); spapr_register_hypercall(H_XIRR_X, h_xirr_x); spapr_register_hypercall(H_EOI, h_eoi); spapr_register_hypercall(H_IPOLL, h_ipoll); object_property_set_bool(OBJECT(icp->ics), true, "realized", &error); if (error) { error_propagate(errp, error); return; } for (i = 0; i < icp->nr_servers; i++) { object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", &error); if (error) { error_propagate(errp, error); return; } } }
static void macio_oldworld_realize(PCIDevice *d, Error **errp) { MacIOState *s = MACIO(d); OldWorldMacIOState *os = OLDWORLD_MACIO(d); Error *err = NULL; SysBusDevice *sysbus_dev; int i; int cur_irq = 0; macio_common_realize(d, &err); if (err) { error_propagate(errp, err); return; } sysbus_dev = SYS_BUS_DEVICE(&s->cuda); sysbus_connect_irq(sysbus_dev, 0, os->irqs[cur_irq++]); sysbus_dev = SYS_BUS_DEVICE(&s->escc); sysbus_connect_irq(sysbus_dev, 0, os->irqs[cur_irq++]); sysbus_connect_irq(sysbus_dev, 1, os->irqs[cur_irq++]); object_property_set_bool(OBJECT(&os->nvram), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_dev = SYS_BUS_DEVICE(&os->nvram); memory_region_add_subregion(&s->bar, 0x60000, sysbus_mmio_get_region(sysbus_dev, 0)); pmac_format_nvram_partition(&os->nvram, os->nvram.size); /* Heathrow PIC */ sysbus_dev = SYS_BUS_DEVICE(os->pic); memory_region_add_subregion(&s->bar, 0x0, sysbus_mmio_get_region(sysbus_dev, 0)); /* IDE buses */ for (i = 0; i < ARRAY_SIZE(os->ide); i++) { qemu_irq irq0 = os->irqs[cur_irq++]; qemu_irq irq1 = os->irqs[cur_irq++]; macio_realize_ide(s, &os->ide[i], irq0, irq1, 0x16 + (i * 4), &err); if (err) { error_propagate(errp, err); return; } } }
SPARCCPU *cpu_sparc_init(const char *cpu_model) { SPARCCPU *cpu; cpu = SPARC_CPU(object_new(TYPE_SPARC_CPU)); if (cpu_sparc_register(cpu, cpu_model) < 0) { object_unref(OBJECT(cpu)); return NULL; } object_property_set_bool(OBJECT(cpu), true, "realized", NULL); return cpu; }