void odm_edca_turbo_check(void *dm_void)
{
/* For AP/ADSL use struct rtl8192cd_priv* */
/* For CE/NIC use struct void* */
/* 2011/09/29 MH In HW integration first stage, we provide 4 different
* handle to operate at the same time.
* In the stage2/3, we need to prive universal interface and merge all
* HW dynamic mechanism.
*/
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO,
"%s========================>\n", __func__);
if (!(dm->support_ability & ODM_MAC_EDCA_TURBO))
return;
switch (dm->support_platform) {
case ODM_WIN:
break;
case ODM_CE:
odm_edca_turbo_check_ce(dm);
break;
}
ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO,
"<========================%s\n", __func__);
} /* odm_CheckEdcaTurbo */
void
odm_edca_turbo_check(
void *p_dm_void
)
{
/* */
/* For AP/ADSL use struct rtl8192cd_priv* */
/* For CE/NIC use struct _ADAPTER* */
/* */
/* */
/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
/* at the same time. In the stage2/3, we need to prive universal interface and merge all */
/* HW dynamic mechanism. */
/* */
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_edca_turbo_check========================>\n"));
if (!(p_dm_odm->support_ability & ODM_MAC_EDCA_TURBO))
return;
switch (p_dm_odm->support_platform) {
case ODM_WIN:
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
odm_edca_turbo_check_mp(p_dm_odm);
#endif
break;
case ODM_CE:
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
odm_edca_turbo_check_ce(p_dm_odm);
#endif
break;
}
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<========================odm_edca_turbo_check\n"));
} /* odm_CheckEdcaTurbo */