Esempio n. 1
0
int __init omap2_clk_init(void)
{
	struct prcm_config *prcm;
	struct omap_clk *c;
	u32 clkrate;

	if (cpu_is_omap242x())
		cpu_mask = RATE_IN_242X;
	else if (cpu_is_omap2430())
		cpu_mask = RATE_IN_243X;

	clk_init(&omap2_clk_functions);

	for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
		clk_init_one(c->lk.clk);

	osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
	propagate_rate(&osc_ck);
	sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
	propagate_rate(&sys_ck);

	for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
		if (c->cpu & cpu_mask) {
			clkdev_add(&c->lk);
			clk_register(c->lk.clk);
		}

	/* Check the MPU rate set by bootloader */
	clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
	for (prcm = rate_table; prcm->mpu_speed; prcm++) {
		if (!(prcm->flags & cpu_mask))
			continue;
		if (prcm->xtal_speed != sys_ck.rate)
			continue;
		if (prcm->dpll_speed <= clkrate)
			 break;
	}
	curr_prcm_set = prcm;

	recalculate_root_clocks();

	printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
	       "%ld.%01ld/%ld/%ld MHz\n",
	       (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
	       (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;

	/*
	 * Only enable those clocks we will need, let the drivers
	 * enable other clocks as necessary
	 */
	clk_enable_init_clocks();

	/* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
	vclk = clk_get(NULL, "virt_prcm_set");
	sclk = clk_get(NULL, "sys_ck");

	return 0;
}
Esempio n. 2
0
int __init omap2_clk_init(void)
{
    struct prcm_config *prcm;
    struct clk **clkp;
    u32 clkrate;

    if (cpu_is_omap242x())
        cpu_mask = RATE_IN_242X;
    else if (cpu_is_omap2430())
        cpu_mask = RATE_IN_243X;

    clk_init(&omap2_clk_functions);

    omap2_osc_clk_recalc(&osc_ck, 0, CURRENT_RATE);
    omap2_sys_clk_recalc(&sys_ck, sys_ck.parent->rate, CURRENT_RATE);

    for (clkp = onchip_24xx_clks;
            clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
            clkp++) {

        if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
            clk_register(*clkp);
            continue;
        }

        if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
            clk_register(*clkp);
            continue;
        }
    }

    /* Check the MPU rate set by bootloader */
    clkrate = omap2xxx_clk_get_core_rate(&dpll_ck, dpll_ck.parent->rate);
    for (prcm = rate_table; prcm->mpu_speed; prcm++) {
        if (!(prcm->flags & cpu_mask))
            continue;
        if (prcm->xtal_speed != sys_ck.rate)
            continue;
        if (prcm->dpll_speed <= clkrate)
            break;
    }
    curr_prcm_set = prcm;

    recalculate_root_clocks();

    printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
           "%ld.%01ld/%ld/%ld MHz\n",
           (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
           (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;

    /*
     * Only enable those clocks we will need, let the drivers
     * enable other clocks as necessary
     */
    clk_enable_init_clocks();

    /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
    vclk = clk_get(NULL, "virt_prcm_set");
    sclk = clk_get(NULL, "sys_ck");

    return 0;
}