Esempi in C++ (Cpp) per omap3_propagate_rate

Esempio n. 1

File: sysconfig.c Progetto: MuMu360121/jordan-kernel

static void dump_omap34xx_clocks(void)
{
	struct clk **c;
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29))
	struct vdd_prcm_config *t1 = vdd1_rate_table;
	struct vdd_prcm_config *t2 = vdd2_rate_table;

	t1 = t1;
	t2 = t2;
#else

	omap3_dpll_allow_idle(0);
	omap3_dpll_deny_idle(0);
	omap3_dpll_autoidle_read(0);
	omap3_clk_recalc(0);
	omap3_followparent_recalc(0);
	omap3_propagate_rate(0);
	omap3_table_recalc(0);
	omap3_round_to_table_rate(0, 0);
	omap3_select_table_rate(0, 0);
#endif

	for(c = ONCHIP_CLKS; c < ONCHIP_CLKS + ARRAY_SIZE(ONCHIP_CLKS); c++)
	{
		struct clk *cp = *c, *copy;
		unsigned long rate;
		copy = clk_get(NULL, cp->name);
		if(!copy)
			continue;
		rate = clk_get_rate(copy);
		if (rate < 1000000)
		{
			PVR_DPF((PVR_DBG_ERROR, "%s: clock %s is %lu KHz (%lu Hz)", __func__, cp->name, rate/1000, rate));
		}
		else
		{
			PVR_DPF((PVR_DBG_ERROR, "%s: clock %s is %lu MHz (%lu Hz)", __func__, cp->name, rate/1000000, rate));
		}
	}
}

Esempio n. 2

File: clock.c Progetto: mozyg/kernel

static int omap3_select_table_rate(struct clk *clk, unsigned long rate)
{
	u8 cpu_mask = 0;
	u32 cur_vdd_rate, current_opp;
	struct vdd_prcm_config *prcm_vdd;
	unsigned long found_speed = 0;
	int ret = -EINVAL;
	int div = 0;

	if ((clk != &virt_vdd1_prcm_set) && (clk != &virt_vdd2_prcm_set))
		return ret;

	if (cpu_is_omap3430())
		cpu_mask = RATE_IN_343X;

	if (clk == &virt_vdd1_prcm_set)
		prcm_vdd = vdd1_rate_table + MAX_VDD1_OPP;
	else
		prcm_vdd = vdd2_rate_table + MAX_VDD2_OPP;

	for (; prcm_vdd->speed; prcm_vdd--) {
		if (!(prcm_vdd->flags & cpu_mask))
			continue;
		if (prcm_vdd->speed <= rate) {
			found_speed = prcm_vdd->speed;
			pr_debug("Found speed = %lu\n", found_speed);
			break;
		}
	}

	if (!found_speed) {
		printk(KERN_INFO "Could not set table rate to %luMHz\n",
		       rate / 1000000);
		return -EINVAL;
	}

	if (clk == &virt_vdd1_prcm_set) {
		ret =
			prcm_get_processor_speed(clk->parent->prcmid,
					&cur_vdd_rate);
		if (ret != PRCM_PASS)
			return -EINVAL;
		current_opp = curr_vdd1_prcm_set->opp;
	} else {
		ret = prcm_get_dpll_rate(clk->parent->prcmid,
						&cur_vdd_rate);
		if (ret != PRCM_PASS)
			return -EINVAL;
		/* Now cur_vdd_rate holds value of core_ck */
		/* The divider for l3_ck */
		ret = prcm_clksel_get_divider((&l3_ck)->prcmid, &div);
		if ((ret != PRCM_PASS) || (div == 0))
			return -EINVAL;
		cur_vdd_rate /= div;
		current_opp = curr_vdd2_prcm_set->opp;
	}

	cur_vdd_rate *= 1000;
	pr_debug("Current rate:%u\n", cur_vdd_rate);
	if (cur_vdd_rate != found_speed) {
		ret =
			prcm_do_frequency_scaling(prcm_vdd->opp,
					current_opp);
		if (ret != PRCM_PASS)
			return -EINVAL;
#ifdef CONFIG_CORE_OFF
		save_scratchpad_contents();
#endif
	}

	if (clk == &virt_vdd1_prcm_set) {
		curr_vdd1_prcm_set = prcm_vdd;
		omap3_clk_recalc(&mpu_ck);
		omap3_propagate_rate(&mpu_ck);
		omap3_clk_recalc(&iva2_ck);
		omap3_propagate_rate(&iva2_ck);
#ifndef CONFIG_CPU_FREQ
		/*Update loops_per_jiffy if processor speed is being changed*/
		loops_per_jiffy = compute_lpj(loops_per_jiffy,
				(cur_vdd_rate / 1000),
				(found_speed / 1000));
#endif
	} else {
		curr_vdd2_prcm_set = prcm_vdd;
		omap3_clk_recalc(&core_ck);
		omap3_propagate_rate(&core_ck);
		omap3_clk_recalc(&core_x2_ck);
		omap3_propagate_rate(&core_x2_ck);
		omap3_clk_recalc(&emul_core_alwon_ck);
		omap3_propagate_rate(&emul_core_alwon_ck);
	}
	return 0;
}