void __init ti816x_init_early(void) { omap2_set_globals_ti816x(); omap_common_init_early(); omap3xxx_voltagedomains_init(); omap3xxx_powerdomains_init(); omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); omap3xxx_clk_init(); }
void __init ti81xx_init_early(void) { omap2_set_globals_ti81xx(); omap3xxx_check_revision(); ti81xx_check_features(); omap_common_init_early(); omap3xxx_voltagedomains_init(); omap3xxx_powerdomains_init(); omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); omap3xxx_clk_init(); }
void __init omap3_init_early(void) { omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); omap2_control_base_init(); omap3xxx_check_revision(); omap3xxx_check_features(); omap2_prcm_base_init(); omap3xxx_voltagedomains_init(); omap3xxx_powerdomains_init(); omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); }
void __init ti81xx_init_early(void) { omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), NULL); omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); omap3xxx_check_revision(); ti81xx_check_features(); omap3xxx_voltagedomains_init(); omap3xxx_powerdomains_init(); omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); omap3xxx_clk_init(); }
void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1) { u8 skip_setup_idle = 0; if (cpu_is_omap24xx() || cpu_is_omap34xx()) pwrdm_init(powerdomains_omap, &omap2_pwrdm_functions); else if (cpu_is_omap44xx()) pwrdm_init(powerdomains_omap, &omap4_pwrdm_functions); clkdm_init(clockdomains_omap, clkdm_autodeps); if (cpu_is_omap242x()) omap2420_hwmod_init(); else if (cpu_is_omap243x()) omap2430_hwmod_init(); else if (cpu_is_omap34xx()) omap3xxx_hwmod_init(); else if (cpu_is_omap44xx()) omap44xx_hwmod_init(); omap_pm_if_early_init(); if (cpu_is_omap2420()) omap2420_clk_init(); else if (cpu_is_omap2430()) omap2430_clk_init(); else if (cpu_is_omap34xx()) omap3xxx_clk_init(); else if (cpu_is_omap44xx()) omap4xxx_clk_init(); else pr_err("Could not init clock framework - unknown CPU\n"); omap_serial_early_init(); #ifndef CONFIG_PM_RUNTIME skip_setup_idle = 1; #endif omap_hwmod_late_init(skip_setup_idle); if (cpu_is_omap24xx() || cpu_is_omap34xx()) { omap2_sdrc_init(sdrc_cs0, sdrc_cs1); #ifndef CONFIG_FB_OMAP_BOOTLOADER_INIT _omap2_init_reprogram_sdrc(); #endif } gpmc_init(); omap2_dm_timer_early_init(); }
static void omap2_init_common_infrastructure_aux(void) { if (cpu_is_omap34xx()) { omap3xxx_voltagedomains_init(); omap3xxx_powerdomains_init(); omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); } else { pr_err("Could not init hwmod data - unknown SoC\n"); } /* ...... */ if (cpu_is_omap34xx()) omap3xxx_clk_init(); else pr_err("Could not init clock framework - unknown SoC\n"); }
void __init omap3_init_early(void) { omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), NULL); omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL); omap3xxx_check_revision(); omap3xxx_check_features(); omap3xxx_prm_init(); omap3xxx_cm_init(); omap3xxx_voltagedomains_init(); omap3xxx_powerdomains_init(); omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); omap_clk_soc_init = omap3xxx_clk_init; }
void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1) { u8 skip_setup_idle = 0; pwrdm_init(powerdomains_omap); clkdm_init(clockdomains_omap, clkdm_autodeps); if (cpu_is_omap242x()) omap2420_hwmod_init(); else if (cpu_is_omap243x()) omap2430_hwmod_init(); else if (cpu_is_omap34xx()) omap3xxx_hwmod_init(); /* The OPP tables have to be registered before a clk init */ omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); if (cpu_is_omap2420()) omap2420_clk_init(); else if (cpu_is_omap2430()) omap2430_clk_init(); else if (cpu_is_omap34xx()) omap3xxx_clk_init(); else if (cpu_is_omap44xx()) omap4xxx_clk_init(); else pr_err("Could not init clock framework - unknown CPU\n"); omap_serial_early_init(); #ifndef CONFIG_PM_RUNTIME skip_setup_idle = 1; #endif if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* FIXME: OMAP4 */ omap_hwmod_late_init(skip_setup_idle); if (cpu_is_omap24xx() || cpu_is_omap34xx()) { omap2_sdrc_init(sdrc_cs0, sdrc_cs1); _omap2_init_reprogram_sdrc(); } gpmc_init(); }
void __init omap3_init_early(void) { omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); /* XXX: remove these once OMAP3 is DT only */ if (!of_have_populated_dt()) { omap2_set_globals_control( OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE)); omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL); } omap2_control_base_init(); omap3xxx_check_revision(); omap3xxx_check_features(); omap2_prcm_base_init(); /* XXX: remove these once OMAP3 is DT only */ if (!of_have_populated_dt()) { omap3xxx_prm_init(NULL); omap3xxx_cm_init(NULL); } omap3xxx_voltagedomains_init(); omap3xxx_powerdomains_init(); omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); if (!of_have_populated_dt()) { omap3_control_legacy_iomap_init(); if (soc_is_am35xx()) omap_clk_soc_init = am35xx_clk_legacy_init; else if (cpu_is_omap3630()) omap_clk_soc_init = omap36xx_clk_legacy_init; else if (omap_rev() == OMAP3430_REV_ES1_0) omap_clk_soc_init = omap3430es1_clk_legacy_init; else omap_clk_soc_init = omap3430_clk_legacy_init; } }
void __init omap2_init_common_infrastructure(void) { u8 postsetup_state; if (cpu_is_omap242x()) { omap2xxx_powerdomains_init(); omap2_clockdomains_init(); omap2420_hwmod_init(); } else if (cpu_is_omap243x()) { omap2xxx_powerdomains_init(); omap2_clockdomains_init(); omap2430_hwmod_init(); } else if (cpu_is_omap34xx()) { omap3xxx_powerdomains_init(); omap2_clockdomains_init(); omap3xxx_hwmod_init(); } else if (cpu_is_ti81xx()) { ti81xx_powerdomains_init(); omap2_clockdomains_init(); ti81xx_hwmod_init(); } else if (cpu_is_omap44xx()) { omap44xx_powerdomains_init(); omap44xx_clockdomains_init(); omap44xx_hwmod_init(); } else { pr_err("Could not init hwmod data - unknown SoC\n"); } /* Set the default postsetup state for all hwmods */ #ifdef CONFIG_PM_RUNTIME postsetup_state = _HWMOD_STATE_IDLE; #else postsetup_state = _HWMOD_STATE_ENABLED; #endif omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); /* * Set the default postsetup state for unusual modules (like * MPU WDT). * * The postsetup_state is not actually used until * omap_hwmod_late_init(), so boards that desire full watchdog * coverage of kernel initialization can reprogram the * postsetup_state between the calls to * omap2_init_common_infra() and omap2_init_common_devices(). * * XXX ideally we could detect whether the MPU WDT was currently * enabled here and make this conditional */ postsetup_state = _HWMOD_STATE_DISABLED; omap_hwmod_for_each_by_class("wd_timer", _set_hwmod_postsetup_state, &postsetup_state); omap_pm_if_early_init(); if (cpu_is_omap2420()) omap2420_clk_init(); else if (cpu_is_omap2430()) omap2430_clk_init(); else if (cpu_is_omap34xx()) omap3xxx_clk_init(); else if (cpu_is_ti816x()) ti816x_clk_init(); else if (cpu_is_ti814x()) ti814x_clk_init(); else if (cpu_is_omap44xx()) omap4xxx_clk_init(); else pr_err("Could not init clock framework - unknown SoC\n"); }