static void __init omap2_gptimer_clocksource_init(int gptimer_id, const char *fck_source, const char *property) { int res; clksrc.id = gptimer_id; clksrc.errata = omap_dm_timer_get_errata(); res = omap_dm_timer_init_one(&clksrc, fck_source, property, &clocksource_gpt.name, OMAP_TIMER_NONPOSTED); BUG_ON(res); __omap_dm_timer_load_start(&clksrc, OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, OMAP_TIMER_NONPOSTED); sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate); if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) pr_err("Could not register clocksource %s\n", clocksource_gpt.name); else pr_info("OMAP clocksource: %s at %lu Hz\n", clocksource_gpt.name, clksrc.rate); }
static void __init omap2_gp_clockevent_init(int gptimer_id, const char *fck_source, const char *property) { int res; clkev.id = gptimer_id; clkev.errata = omap_dm_timer_get_errata(); /* * For clock-event timers we never read the timer counter and * so we are not impacted by errata i103 and i767. Therefore, * we can safely ignore this errata for clock-event timers. */ __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); res = omap_dm_timer_init_one(&clkev, fck_source, property, &clockevent_gpt.name, OMAP_TIMER_POSTED); BUG_ON(res); omap2_gp_timer_irq.dev_id = &clkev; setup_irq(clkev.irq, &omap2_gp_timer_irq); __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); clockevent_gpt.cpumask = cpu_possible_mask; clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); clockevents_config_and_register(&clockevent_gpt, clkev.rate, 3, /* Timer internal resynch latency */ 0xffffffff); pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name, clkev.rate); }
/** * omap_timer_init - build and register timer device with an * associated timer hwmod * @oh: timer hwmod pointer to be used to build timer device * @user: parameter that can be passed from calling hwmod API * * Called by omap_hwmod_for_each_by_class to register each of the timer * devices present in the system. The number of timer devices is known * by parsing through the hwmod database for a given class name. At the * end of function call memory is allocated for timer device and it is * registered to the framework ready to be proved by the driver. */ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) { int id; int ret = 0; char *name = "omap_timer"; struct dmtimer_platform_data *pdata; struct platform_device *pdev; struct omap_timer_capability_dev_attr *timer_dev_attr; pr_debug("%s: %s\n", __func__, oh->name); /* on secure device, do not register secure timer */ timer_dev_attr = oh->dev_attr; if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) return ret; pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); if (!pdata) { pr_err("%s: No memory for [%s]\n", __func__, oh->name); return -ENOMEM; } /* * Extract the IDs from name field in hwmod database * and use the same for constructing ids' for the * timer devices. In a way, we are avoiding usage of * static variable witin the function to do the same. * CAUTION: We have to be careful and make sure the * name in hwmod database does not change in which case * we might either make corresponding change here or * switch back static variable mechanism. */ sscanf(oh->name, "timer%2d", &id); if (timer_dev_attr) pdata->timer_capability = timer_dev_attr->timer_capability; pdata->timer_errata = omap_dm_timer_get_errata(); pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), NULL, 0, 0); if (IS_ERR(pdev)) { pr_err("%s: Can't build omap_device for %s: %s.\n", __func__, name, oh->name); ret = -EINVAL; } kfree(pdata); return ret; }
static void __init omap2_gp_clockevent_init(int gptimer_id, const char *fck_source, const char *property) { int res; clkev.errata = omap_dm_timer_get_errata(); /* * For clock-event timers we never read the timer counter and * so we are not impacted by errata i103 and i767. Therefore, * we can safely ignore this errata for clock-event timers. */ __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property, OMAP_TIMER_POSTED); BUG_ON(res); omap2_gp_timer_irq.dev_id = &clkev; setup_irq(clkev.irq, &omap2_gp_timer_irq); __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC, clockevent_gpt.shift); clockevent_gpt.max_delta_ns = clockevent_delta2ns(0xffffffff, &clockevent_gpt); clockevent_gpt.min_delta_ns = clockevent_delta2ns(3, &clockevent_gpt); /* Timer internal resynch latency. */ clockevent_gpt.cpumask = cpu_possible_mask; clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); clockevents_register_device(&clockevent_gpt); pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n", gptimer_id, clkev.rate); }